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Re: Protecting a CMOS gate input
Jasen Betts wrote:
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It looks like you could make it oscillate when the button is held, or  
not, by changing the resistor ratio.




Re: Protecting a CMOS gate input
On 16/05/2020 03:02, Pimpom wrote:
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The CD4013 specifications require that the maximum rise time of the  
clock signal is 10us at VDD10%V and 5us at VDD15%V so I would assume  
that you need to meet 5us to be safe, for VDD12%V.

Depending on what series resistor you add, shunt capacitance etc. you  
may struggle to meet that, and it is worth checking. Also it may get  
worse over time if the switch contacts oxidise. If cost is not critical  
then you could add a Schmitt trigger buffer before the clock input.

Re: Protecting a CMOS gate input
Not sure I know what a bistable chip is, but I often use optocouplers when  
connecting microcontroller port pins to the outside world.  Of course, that
 approach limits you to one-way in or out of the chip.  (And the de-bounce  
can usually be done in software.)


Re: Protecting a CMOS gate input
On 5/15/2020 7:28 AM, mpm wrote:
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Using an ADC is a valid way to read button states, too. I can take a 8  
pin AVR with 3 or 4 ADCs on board and an LM324 to buffer the voltage and  
protect whatever is on the other side and multiplex 15 or 20 buttons,  
using the buttons to switch in resistors in a divider to the ADCs and  
thresholds set in software.

A moving-average filter/sample binning + state machine prevents any  
bounce-glitches it's a very solid arrangement.

Re: Protecting a CMOS gate input
On 5/15/2020 9:00 PM, bitrex wrote:
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Er, protect the uP inputs, getting my circuits confused :)

Re: Protecting a CMOS gate input
On 15/05/2020 11:53, Pimpom wrote:
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The schottky diodes may well be superfluous depending on the value of  
series resistance. If R is high enough to keep highest expected surge  
voltage well below input ESD diode latch-up trigger current. The  
parallel C has to be large enough to limit rise time to least many ns  
for the diodes to begin forward conduction. Since the input is from a  
push button and the input is not edge rate critical you can afford to  
massively overdo the series R and shunt C. You haven't mentioned having  
a pullup or pull down resistor, generally pushbutton contacts need at  
least 100uA "wetting" current to ensure reliable operation.

piglet


Re: Protecting a CMOS gate input
On Friday, 15 May 2020 14:26:16 UTC+1, piglet  wrote:
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If you prefer to avoid schottky diodes then BAV99 or BAV99W dual silicon
diodes work well in this sort of application (with some resistance
between the diodes and the gate input as well as the input series
resistor before the diodes.

John

Re: Protecting a CMOS gate input
wrote:

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Little resistors can arc over, given a good ESD zap.

Some connectors are a lot better than others, in that they connect
ground first.



--  

John Larkin         Highland Technology, Inc

Science teaches us to doubt.

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Re: Protecting a CMOS gate input
On 16/05/2020 02:08, snipped-for-privacy@highlandsniptechnology.com wrote:
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Yes. It would be worthwhile to use a resistor rated for several kV (some  
are inexpensive) or tested and found to usually survive and also not arc  
over and thereby carry more current than Ohm's law would predict.

By putting the incoming signal trace close to a big ground pour on the  
PCB and removing a small region of solder mask, you could make a spark  
gap that will arc over at a few kV to shunt the ESD before it reaches  
the series resistor, and provided the resistor can take more than the  
voltage at which the spark gap arcs over, the resistor ought to be safe.  
You can of course buy spark gaps and gas discharge tubes, if the parts  
budget permits.



Re: Protecting a CMOS gate input
On 2020-05-15 09:26, Piglet wrote:
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Yup.  1 uF will turn a 20 kV HBM spark into 2 volts.  I use that  
approach with diode lasers quite a lot.

Cheers

Phil Hobbs


--  
Dr Philip C D Hobbs
Principal Consultant
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Re: Protecting a CMOS gate input
On Friday, May 15, 2020 at 12:14:44 PM UTC-4, Phil Hobbs wrote:
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g
'd
d
  
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Yes, but he is talking about plugging in a cable with who knows what potent
ial on it.  It can be a lot more capacitance than the HBM.  The HBM and oth
er models are intended to be approximations to some set of conditions that  
may or may not represent actual conditions of any given use case.  If I am  
not mistaken, the HBM spark is just that, a spark where much of the energy  
is dissipated into the spark rather than the equipment... or do I have it w
rong?  The surge from the actual contact with a conductor may well deliver  
a lot more energy than the HBM.  

It has been a while since I worked with this stuff but I seem to recall the
 peak voltage, peak current and peak power were not all related directly si
nce the load responds in a non-linear way.  The bottom line is an ounce of  
prevention is worth a pound of "oh, crap!"  I'd rather overdesign than unde
r design protection.  

I think I would use a series resistor, a Zener diode and a capacitor, possi
bly on a separate board or at least an isolated ground region, to prevent g
round current surges from disrupting the operation of the circuit.  I also  
would not use a CMOS device as the first active device.  Even with their bu
ilt in protection they are too easily damaged.  Running from one board to a
nother in the same cabinet is one thing.  From something on the other end o
f an external cable is another.  

--  

  Rick C.

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Re: Protecting a CMOS gate input
On 5/15/2020 6:56 PM, Piglet wrote:
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Here's some data:
Vdd is 12V. Series R is tentatively 10k with a parallel R of 100k  
which is also the pull-down resistor. Parallel C to be decided.

Re: Protecting a CMOS gate input
wrote:

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,
If a long unshielded cable to the pushbutton is used, it is going to
pick up RFI, especially since the pushbutton is open circuit most of
the time.  

Make sure you bypass any RF entering rom the cable into your device,
before it hits any semiconductors. Do not let the RF current
circulate around the PCB, filter it out close to the cable socket.
These days the low pass filter should work well for at least from 0,1
MHz to several GHz to get rid of any AM broadcast and smart phone
signals.

The GSM cellular phone signal is TDMA and if is rectified in an
oxidized cable connector or some protection diodes, it will generate a
square wave of a few hundred Hertz, which could misfire the flip-flop.


Re: Protecting a CMOS gate input
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The FF has at least 4V of noise immunity. That would take quite the cell phone. ;)

Cheers

Phil Hohhs

Re: Protecting a CMOS gate input
On Friday, May 15, 2020 at 5:04:57 PM UTC-4, snipped-for-privacy@gmail.com wrote:
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phone. ;)

Won't the signal induce a current proportional to the loop size so that the
 resulting voltage will then be dependent on the input resistance?  The dev
il is always in the details.  That's why experts get called in to solve the
se sorts of problems.  Often it is not a matter of black magic, but of bein
g meticulous.  

The circuit is running from 12 volts, so lots of noise margin, but also the
 circuits are high impedance.  Damned if you do, damned if you don't.  

--  

  Rick C.

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Re: Protecting a CMOS gate input
On Fri, 15 May 2020 14:04:53 -0700 (PDT), snipped-for-privacy@gmail.com wrote:

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For CD4013, the noise margin at Vdd=5 V is quoted as 1 V and at Vdd15%
V as 2.5 V.

Consumer electronics is suppose to withstand a 3 V/m field strength
without malfunctioning.

A random wire several wavelengths long will capture about similar
voltages as a 1/4 wavelength monopole. A 1/4 wave monopole at 900 MHz
is about 0.1 m, so 3 V/m will induce 0.3 V into the wire. This is for
the far field. When the transmitter is in the near field, the voltage
can vary significantly.


Re: Protecting a CMOS gate input
On 2020-05-16 03:21, snipped-for-privacy@downunder.com wrote:
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CMOS logic threshold is very roughly between 1/3 and 2/3 of VDD.


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But you have to rectify it before it can cause logic problems in  
dog-slow 4000-series CMOS.  Good luck getting volts of rectified signal  
from an input diode.

Cheers

Phil Hobbs

--  
Dr Philip C D Hobbs
Principal Consultant
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Re: Protecting a CMOS gate input

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If you expect/experience static discharges, the network might avoid
failures. Best to not expose any semiconductor the the outside world.

If you expect ESD zaps to change the state of a cross-coupled gate
flop, put a cap on one output to ground.



--  

John Larkin         Highland Technology, Inc

Science teaches us to doubt.

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Re: Protecting a CMOS gate input
On 5/15/2020 8:45 PM, snipped-for-privacy@highlandsniptechnology.com wrote:
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I thought I'd place a resistor across the switch contacts, high  
enough not to cause triggering, low enough to prevent static  
build-up.


Re: Protecting a CMOS gate input
On Saturday, May 16, 2020 at 2:32:34 AM UTC-4, Pimpom wrote:
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I'm more worried about when the cable is plugged in.  I recall plugging in  
audio jacks to music amps and getting the big hum blast.  The guy whose equ
ipment it was would yell at me.  

I guess cabling problems are more of a problem when dealing with cabling di
fferent chassis together.  Then you have ground differences and lots of thi
ngs can be a problem.  Plugging in a remote switch might be a lot less of a
n issue if it isn't grounded to anything.  

--  

  Rick C.

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