I have learned power electronics in university. But now i have to design a prototype. Is there any good book or application note tell me how to design a prototype. Thank you very much!
practical tips on SMPS design
Sep 30, 2005
6 Replies
Is that LTC's an70, the low-noise SMPS app note? BTW, are you sufficiently set-up yet to work on my low-noise power supply?
Thanks,
- Win
One would assume it's LTC's app note (the one that has the amusing flowchart in the front).
IMO, LTC has some of the best app notes / documentation in the SMPS arena.
Cheers
PeteS
AN70 is a good application note
martin
Did you make any progress on it?
I've toyed half a day with Tony's two cores idea for the low parasitics, with dual apertures cores that I have at hand (EPCOS B62152-A4-X30, AL=10uH).
primary 2x2T interm. 1T secondary 2x2T
measured leakage ind = 260nH primary/secondary parasitics = 2.5-3.5p
I'll resonate Lleak on the 1 turn link between the 2 cores at 4.5MHz with
18nF. Fixed frequency switching at 4.5MHz. Core walking is prevented with an external DC balancing current source scheme I already used in a similar case (12Vpp 500kHz Manchester data + 24Vpp 8kHz sinus for supplying the remoted device on an EP13 core). Rectification = 4 x 1N5817 5V supply, +/-4.5V output, 2x25R load = 1.8W square wave driven.Sims are encouraging:
86% efficiency and probably 80% final (excl. mosfets driving and controler). At fixed 100% duty cycle the output impedance is 0.8R and the coupling impedance between the outputs is 0.6RI don't have adequate mosfets and the schotkies to try it fast, but I'm confident it should work nicely. I may have to use it in the coming weeks, so we'll know.
In order to reduce the coupled common mode voltage I also think it'd be nice to center tap the intermediate winding with 2x47p caps or something refered to the primary side GND.
Any other idea?
Thanks,
Fred.
In message , Fred Bartoli writes
Can you get a fine coax through the cores?
One turn each, join the inners to form the loop. For signal handling connect each screen to it's respective 0v and for power handling have a continuous screen, connected to primary 0v.
My old boss would also earth each core to it's own 0v, usually with a strap of 26-gauge tinned copper over the outside of the core.
Tony Williams
"Tony Williams" a écrit dans le message de news: snipped-for-privacy@ledelec.demon.co.uk...
nice
refered
Good idea! The coax has to be pretty fine (hole diameter=3.4) but RG178 or RG179 should fit in together with the dual 2 turns 0.2mm windings. The cross coupling cap should be about 4p for the RG178 and 3p for the RG179, so no pb on this side. The leakage inductance will increase though, but I should be able to tune it out correctly, so probably no pb here.
Better than the dual 47p which was estimated to require a 20mA pk current.
Let pass some time...
Hmmm... thinking a bit more... The screen loop can't be closed: it'll become the winding turn. I now think there's finally no advantage (for a one turn winding) to go the coax route: same voltage induced into the shield than into the center conductor. Even more the parasitic capacitance will probably increase.
If I can find a small piece of these coax (hey the plural patrols, how do you make the plural mark on this one?) without buying an whole roll I'll make a comparison, just to make sure.
I'll probably strap the cores with the sticky copper foil used to solve EMC problems: stick it to the core and solder on ground plane. Better shielding and the cores are guaranteed to not move.
Thanks,
Fred.
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