Possible PLL Lock Indicator?

Looks interesting, and is probably a decent solution unless the reference has any significant slew or noise. In lower-SNR applications, the peak phase error can be an appreciable fraction of a radian and the loop still tracks quite happily.

My fave for that is to use an auxiliary PFD on the I phase and look for its output to be within ~10% of the rails.

Cheers

Phil Hobbs

Well, that is the auxiliary early-late thing that I suggested.

The small delay windows assume that the main loop will always run at very low edge-time error. If the loop is completely unlocked and the edges are walking across one another, that circuit will make a false briefish "locked" blip periodically.

Any lock detector needs some analog or digital time delay after the basic decision circuit.

If you were willing to nudge the main PLL a little, wigwag it at low frequency, a single early/late flop (even the main d-flop phase detector) output could be observed for correlation to the wiggle. Sort of a lock-in amplifier. That would demonstrate true causality in the PLL, not just accidental alignment. Maybe.

Absolutely true. It is easy to add a delay circuit to a PFD to determine the minimum time between clock and data and trigger the lock detect.

However, this doesn't help if the loop is far from lock and going through the slipping cycles. So you have to wait until things settle before you start measuring the lock error.

How do you decide that things have settled?

I should have expressed additional constraints...

I'd observe for x-cycles with no blips before I'd call it locked (already done that with another lock detect approach... counters are cheap in chip-land ;-)

This was aimed at PFD applications, NOT analog PD's. With analog PD's you'll need some filtering... your quadrature approach helps that. ...Jim Thompson

Easy. Measure the time between false lock indications. When it exceeds some predetermined time interval, start looking for lock.

A far better approach is to lock the victim PLL to the correct frequency before attempting to lock to the desired phase.

I used this to achieve closure in numerous clock track generators for servo writers for the IBM 3330 and Winchester production systems. I could achieve lock in less than 60 seconds to a very tight detection threshold, where competing products took many hours to achieve closure, if they succeeded at all.

I made a lot of money on this concept.

But you have to know how to make a good PLL.

On a sunny day (Sun, 15 Oct 2017 22:32:25 GMT) it happened Steve Wilson wrote in :

Indeed, that is how the Ampex quadruplex head rotation servos worked. Even in tube days...

Since we ah...know...that if the phase is locked to something within a radian the frequency will be locked as well, could you look for a consistent frequency lock over some period of time?

Say two synchronous counters clocked from the VCO and reference, terminal count outputs ANDed and clocked into latch which if high increments a third counter to indicate the frequency was locked over that interval. A low output causes all the counters to be reset and start again on whichever terminal count fired first. Trigger the lock indicator after the third counter has been fired X number of times

Any lock-detection scheme that involves turning a low-SNR analogue signal i nto logic levels is doomed for at least two reasons, both connected to dete ction bandwidth.

The first is capture effect. Taking the sum of two (reasonably narrowband) waveforms and applying amplitude limiting preserves the zero-crossing rate of the stronger of the two. With two sine waves of similar frequency, the e ffect is very sharp--a fraction of a dB is enough.

With noise the effect is more gradual. At SNRs below about 10 dB, noise dro pouts start to be annoying. Below that, they rapidly increase until near 0 dB the signal disappears entirely.

Note that this is the SNR in the full input BW. That brings us to the secon d reason: bandwidth. The input BW has to accommodate the lock range of the PLL, which is ordinar ily far wider than the loop bandwidth.

It's the SNR within the loop BW that governs analogue PLL performance. An a nalogue loop can do an excellent job of pulling out narrowband signals 20 d B below the wideband noise, sometimes much more.

Thus in those sorts of situations the lock detector has to be looking at th e loop itself.

That's why you use a second PD in the other phase as a lock detector--when the loop is unlocked the DC component goes away.

Cheers

Phil Hobbs

Analog phase detectors are superior for noisy signals...

Twist on a Howland Charge Pump:

OpAmp equivalent of the classic S-curve discriminator:

(PDF's on my website, near bottom of Home Page.)

That discriminator might work as an auxiliary _frequency_ detector to aid acquisition? ...Jim Thompson

If you're recovering data, sometimes you can validate the data itself as the lock detector. Things like frame structures, CRCs, 8b10b violations, Manchester pattern, stuff like that. If the data looks bad enough, kick back into acquisition mode.

Well, measuring what you care about is usually a good thing, sure.

Here you lose me. If you're close enough that much more than 50% of the data come out right, seems like you have to be in lock already, no?

Cheers

Phil Hobbs

Good point. ...Jim Thompson

We have some products that recover a fiberoptic data stream. If the data looks like nonsense, we go into wide bandwidth loop mode, which should achieve lock if it can be done. Once the data looks sensible, we go to narrowband mode to reduce jitter. This is a system where we want to recover a good clock, as well as the data itself.

We have some products that recover a fiberoptic data stream. If the

At reasonable SNR. In low-SNR situations widening the loop BW will prevent it from locking at all, whereas a sufficiently-slow sweep will still work.

Since that's pretty hard to do if the SNR isn't decent to begin with, that approach ought to work fine.

Cheers

Phil Hobbs

Or very narrow bandwidth... slo-o-ow, but effective... I've acquired TACAN from signals so noisy you couldn't (on a 'scope) recognize that anything was there... just has to be wide enough bandwidth to cope with Doppler. ...Jim Thompson

Trouble is that the pull-in time is quadratic in the frequency error, which gets old pretty fast. It's also vulnerable to false lock.

Cheers

Phil Hobbs

What's your definition of "false lock"?

(When I was first dabbling in PLL's I didn't know a zero was needed. The lock was so slow I gave up and went to lunch with Tom Frederiksen. When we came back it was locked. Took me awhile to figure out that the "big-ass" electrolytic I used had substantial ESR ;-)

Then I bought Gardner's book ;-) ...Jim Thompson

The pull-in mechanism depends on the residual beat note coming out of the l oop filter, as I mentioned several posts ago. If the filter phase is asympt otically 0 (a simple lead/lag or an integrator with a series resistor), the n on the ripple half cycle that points towards lock, the ripple reduces the beat frequency. That half-cycle therefore lasts slightly longer, producing a DC component that nudges the loop towards lock.

If the filter phase is asymptotically -180 degrees, because we added anothe r couple of poles way out beyond the loop BW to reduce ripple sidebands, th e pull-in signal becomes a "push-out" signal and the loop won't lock unaide d.

In more complicated situations, you can have beat-frequencies where the pul l-in signal goes through a (stable) zero, so the beat note stays roughly co nstant. That's false lock.

Cheers

Phil Hobbs