Hi All I=92m going to design a PLL for the frequency of 622.08MHz. This PLL should support external feedback. I=92ve looked for such PLL muck but I haven=92t found . What shall I do if such a PLL doesn=92t exist? I know that there is many =93phase and freq. detector=94 and VCXO from different vendors but I don=92t know how to design Loop filter and charge pump. Is there any IC that integrates phase-frequency detector, loop filter and charge pump? I=92ll very appreciate anyone who helps me.
I think you need to give more details of exactly what you want to do. You want a 622MHz output, do you want to lock to a 622MHz input or are you going to use a lower reference frequency and a divider?
Wait, I thought that was what you were supposed to do once you found a PLL that *could* conceivably work, and had to start making it do so rather than being able to tell your boss it really was impossible?!
...or Best's book, "Phase-Locked Loops" is a good beginning-/intermediate-level text.
...or the ubiquitous ADF43xx series from Analog Devices.
My guess is that it is either clock generation or clock recovery for SONET/SDH STM4 or wide area gigabit ethernet.
Telephone company stuff generally syncronises everything to a master clock from a central office. Ocasionally you hear storys of some little telecomms company that used a link from a competitor as the clock source for their entire network, until one day...
A VCO module such as the one on ebay that you mentioned could form a part of a PLL to recreate a clock from another souce.
The original message appears to have come from Iran College of Tele-communications in Tehran so the OP is most likely a clueless student, could be a useless acadaemic.
Dear Bob Is it important that who am I and What I'm doing !!! Yes I am Iranian and doing SONET project. But I'm not clueless and not in "way out of his league". You are impolite. Would you please tell me what is wrong whit the answer that I made?
Dear Bob Is it important that who am I and What I'm doing !!! Yes I am Iranian and doing SONET project. But I'm not clueless and not in "way out of his league". You are impolite. Would you please tell me what is wrong whit the post I've sent?
Dear Bob. Is it important that who am I and What I'm doing!!! Yes I am Iranian and doing SONET project. But I'm not clueless and not in "way out of his league". You are impolite. Would you please tell me what wrong with the post I=92ve sent is?
Usenet newsgroups like this one tend to be fairly bruising places. Don't take it too personally, that's just how it is. Being called clueless if you don't specify your problem very well is actually relatively gentle treatment, for Usenet. It's a very masculine environment, though we do have the occasional apparent female like our recent acquisition Sylvia, who seems to have no problems holding her own.
This is a great place to get good quality help, free, from some pretty smart and experienced engineers. It's also a good place to collect abuse from the collection of nutcases, wannabees, and egomaniacs that also post here. (There's significant overlap between all four categories, so you shouldn't necessarily ignore someone just because he yells obscenities at odd moments or says distasteful things about politics or religion.)
The problem is that your post didn't demonstrate that you'd actually thought about the problem before asking. The reason that people like to help here is that it's fun, and they have a chance to think about some interesting engineering problems that aren't what they're working on right now. As the old proverb puts it, "a change is as good as a rest."
Uninformed questions from people who haven't apparently put in much effort are not fun, and are too much like what we face daily at work. Note that this does *not* mean that you have to be an expert already, you just have to show that you've done some serious thinking on your own. The group sci.electronics.basics is for beginner questions, e.g. "How does a PLL work?"
I suggest doing something like this:
Calculate or read up on what your jitter requirements are. Communications is actually a pretty stringent application, so there's lots of data out there.
Transform that jitter spec into a frequency-domain specification for phase noise vs. frequency, so you know what sort of problem you're facing.
Do a trial design with whatever you have on hand or can find in catalogues, calculate its performance using ordinary feedback theory, and compare the results with (2).
4a. If you made it, you're done--if the design has interesting features, tell us about it and join the regulars here. People who can do that sort of thing are very welcome.
4b. If you didn't make it, ask a question like "I designed this SONET clock recovery loop but it's 20 dB (insert actual measurement or calculation here) worse than the spec of -120 dBc/Hz at 100 Hz offset (insert actual numerical specification here). I have lots of loop gain and the phase detector should be easily quiet enough. Do you have any idea what might be wrong?"
You'll get some helpful answers and maybe some abuse, but remember that the helpful people are treating your skills with respect and the abusive ones don't know you personally at all. Either way, if you really aren't clueless, come join in and help us educate the ones who are. I've recovered from cluelessness several times myself. ;)
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