Feedback loops bug me

Hi:

I have a PLL loop which works. But I sit here looking at my LTspice AC analysis schematic and try to trace signals around it from the reference phase source into the PFD, to the feedback phase from the VCO (a motor in this case) and it's just so confusing.

At DC, the thing has positive feedback! That is, due to the action of the phase error integrator (a 2nd order PLL), as well as the integration of frequency->phase which occurs in the VCO, a low frequency up wiggle into the + input of the PFD comes back from the motor as a down wiggle. But that goes into the - input of the PFD. So that would cause more up-ness at the output of the PFD than what arose from the original up wiggle that started the whole thingy.

That means it has positive feedback.

Only at the unity gain frequency of the open loop (f0) does it have negative feedback, and even then only with about 55 degrees of margin.

That is what is so counter-intuitive. A loop can have positive feedback at a frequency where gain is very high, and yet be stable as long as at f0 it's phase is just not too close to positive feedback. In fact, with

55 degrees of margin, it's close to positive feedback than negative.

Then this is even more funny: A loop can be stable with 90 degrees phase. What is that? Half way to negative feedback, or halfway to positive feedback?

Ugh!

--
Good day!

________________________________________
Christopher R. Carlen
Principal Laser&Electronics Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and
"BOGUS" from email address to reply.
Reply to
Chris Carlen
Loading thread data ...

Sounds like you are deluding yourself ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Positive feedback will latch! Maybe the real thing locks on the opposite clock phase from the one you're simulating. Lots of pll's will just slip a half cycle if you flip the loop gain polarity.

John

Reply to
John Larkin

Yep, an EXOR or multiplier-type phase detector will do that.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Tch tch tch. You're trying to think rationally about infinities, without doing all the math.

In the frequency domain, at DC, the phase shift is undefined. Why? Because the gain is infinite. You can only discover the phase shift as you _approach_ DC.

So you have to toss the frequency domain out the window for this thought experiment (but not for analyzing the loop). To understand things you have to go back home, to the time domain where we all live and things make sense.

Here, if the phase of the motor lags a bit the integrator in your loop filter will act to drive the motor harder, which will spin faster, which will make it accumulate phase faster -- so indeed you have negative feedback because a slow motor tends to speed up.

If you try to go forward at this point you immediately run into problems because of the lag caused by the double integrator. Trying to describe the system behavior, and discovering stability, entirely in the time domain is fiendishly difficult. It can be done, in fact it must be done if you system is severely nonlinear, but it isn't pretty.

So to actually discover stability you use the frequency domain, and there you find lots of things that are counter intuitive. There are several ways you can cope with this problem:

  1. Become a digital system designer.
  2. Enter a convent (or a monastery if you're boring).
  3. Get an MBA, and become a pointy-haired boss.
  4. Just do the math in the frequency domain, and trust it.
4a. Do the math in the frequency domain, and insist on doing it until it all becomes intuitive. Internally, this means that those neurons in your brain that _know_ that it's all BS will have to be killed off before you can proceed -- this is why good engineering students drink so much beer.

Keep thinking on this, tell yourself it doesn't matter, and DRINK MORE BEER!

Or consider that at 55 degrees of phase margin your 'positive' feedback is 1/2 or so -- which means that after it rolls through the loop once it's 1/4, then 1/8, then 1/16, etc.

But wait! A loop can be _unstable_ with 90 degrees phase shift at unity gain -- and it can be either +90 or -90 degrees (I just know someone is going to challenge me on that, and I'll have to fake up some bizarre loops, but it's true -- really).

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html
Reply to
Tim Wescott

Do this thought experiment (and consider my previous post, and how much beer you have on hand).

Replace your integrators with really, really low-pass filters. At all but the lowest of frequencies they'll each cause -90 degrees of phase shift, and your feedback will be positive. Right at DC, however, they'll have 0 degrees phase shift and your feedback will be negative (and very large), just like you want.

-- snip --

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html
Reply to
Tim Wescott

No. It works exactly as it should. It uses a 3-state PFD. There is negative feedback in the sense that observation shows the following:

  1. If reference phase increases
  2. output of PFD increases
  3. output of compentation network (VCO command voltage) increases
  4. VCO therefore speeds up
  5. phase error between VCO and ref therefore decreases
  6. phase of VCO goes into - input of PFD, so
  7. PFD output decreases
  8. When VCO has caught up to ref, then PFD output returns to zero

What is confusing is that in the open loop AC analysis (1) there is 180 degrees of phase shift to the - input of the PFD. That would seem to be positive feedback.

The 180 comes from the two integrating poles (1/s) from the phase error integrator and the VCO.

Note:

  1. That means the - input to the PFD is grounded, and the output of the VCO is where the frequency response is being measured. This is an
***AC*** model so the output of the VCO means Kvco/s .
--
Good day!

________________________________________
Christopher R. Carlen
Principal Laser&Electronics Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and
"BOGUS" from email address to reply.
Reply to
Chris Carlen

Which is 180 degrees, with ideal components.

Yes, that is obvious. Without thinking about phase shifts, inspection of the loop reveals negative feadback. The confusion arises in why the AC shows 180 degrees.

Yeah, that's what I mean.

Adding your stuff from the later post:

"Do this thought experiment (and consider my previous post, and how much beer you have on hand).

Replace your integrators with really, really low-pass filters. At all but the lowest of frequencies they'll each cause -90 degrees of phase shift, and your feedback will be positive. Right at DC, however, they'll have 0 degrees phase shift and your feedback will be negative (and very large), just like you want. "

Yeah, certainly it actually works out that way since the integrator fades out as the opamp gain is finite.

I wouldn't mind seeing such a loop.

I think I have to progress to the root-locus method of analysis.

Good day!

--
_____________________
Christopher R. Carlen
crobc@bogus-remove-me.sbcglobal.net
SuSE 9.1 Linux 2.6.5
Reply to
CC

Consider yourself challanged!

I can think of an example where this is true, but its a cheat.

Consider a response where the gain falls down past unity, hitting unity at 90 degrees. Then have the gain increase back up again to some value above unity. Then have the gain fall off at a >= second order rate back through a final unity gain. This will be unstable. However, the 1st x-ing is a red herring. Stability only cares about the final x-ing, not intermediate ones.

Other than that, there is no realistsic way for the system to be unstable if gain < 1 at phase < 180. The converse is not true. Its quite easy to construct systems with gain > 1 at 180 deg (net positive fb) that are quite stable.

Of course, one has to have a correct value of small signal loop gain, at all operating conditions. In non-linear systems, the small signal gain at one output value, is not the same as at another output value. For example, the collecter base capacitance of a transister is a function of collecter base voltage. This can cause different phase shifts at different output voltages, hence intability at only some values of output. One needs to construct ac gains over a range of values, even this, technically isnt enough. In principle, its possible for, say an amp, to be stable ac analysis wise when the amp is say, in clip and out of clip, but not if transferring between those two regions.

The only way to verify stability is to actually do many transient runs in spice (with good models). AC analysis or hand calculations are just not sufficient for anything but trivial circuits.

Kevin Aylward B.Sc. snipped-for-privacy@anasoft.co.uk

formatting link
SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

"There are none more ignorant and useless,than they that seek answers on their knees, with their eyes closed"

Reply to
Kevin Aylward

Isn't this almost a case of effectively separate circuits? I mean that say in a transistor stage, if there is a unity gain point at some frequency where the crossing phase is Other than that, there is no realistsic way for the system to be

What exactly are the criteria for stability? In my not-formally derived understanding (a lot of which came from AoE's PLL and opamp discussions) negative FB at DC and

Reply to
CC

I would say this is a matter of properly modeling the stage, rather than separate circuits. We can ignore certain properties of devices if we constrain the analysis, but you can't really see what contraints (loop frequency max, for example) to apply until you know what demons lurk out there. There are certainly good rules of thumb, but they remain that ;)

I have had a particular circuit (SMPS, in this case) that was unstable at 150 degrees (30 degrees margin), but that was an unusual case. (Current mode supply with loads ranging from zero to 15 amps with fast transients).

For most of them, it can be - it depends on the loop. If there are severe non-linearities involved, no.

I made myself a nice little program that plots phase v. load at arbitrary frequencies and then plots it as a rolling movement. Very handy to see just where the phase becomes an issue. Of course, with very fine-grained discrete frequencies, it can take a while to run ;)

Many threads here have noted that layout is a critical issue in loops because it's easy to introduce an unintended pole or zero by the artifice of a track being too close to a high current plane. Myriad of these examples abound.

Remember : Drink more beer!

Cheers

PeteS

Reply to
PeteS

In message , dated Sat, 12 Aug 2006, CC writes

As far as it goes, yes, but it doesn't go far enough. The Nyquist Diagram is a polar plot of gain and phase. The crunch point is at (-1,

0) which represents unity gain and 180 phase. The plot must not *enclose* this point, because if it does, the plot will pass through it during switch-on, resulting in oscillation that may or may not be sustained.

As Kevin A said, there are other cases. if you drive the circuit into non-linearity, its gain goes down, perhaps to zero, over part of a cycle. This also may make the plot pass transiently through (-1, 0), resulting in parasitic oscillation, which, again, may be sustained or may stop.

This is a different approach; don't try to mix them up. Of course, they are related, but that isn't elementary. Poles and zeroes live on a different plane than the Nyquist diagram, even though both of them have real and imaginary axes.

--
OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk
2006 is YMMVI- Your mileage may vary immensely.

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK
Reply to
John Woodgate

In article , Chris Carlen wrote: [...]

If this what you really have, the phase shift is 179.9999 degrees not 180 degrees and it will ring like a bell. The integrator's imperfection is all that is making it stable. Is there a resistor in series with the capacitor?

--
--
kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

In article , Tim Wescott wrote: [....]

What matters is the phase shift at the highest frequency where you have unity gain. A system that includes a delay line can cycle above and below unity gain many times before it finally stays below.

Also: You have to be careful about not dropping 360 degrees from the phase shift. If a circuit is already an oscillator, enclosing it in a feedback loop may not stop the oscillation. If you drop the 360 degrees in the Bode plot, it can look like it should when it won't.

--
--
kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

Yes. And a lead-lag network. The transient response is quite good. There is about 3dB of gain peaking in the closed-loop.

Here's the circuit AC and transient models in LTspice form:

formatting link

--
_____________________
Christopher R. Carlen
crobc@bogus-remove-me.sbcglobal.net
SuSE 9.1 Linux 2.6.5
Reply to
CC

That makes it just about ideal. In time domain, there should be nearly no overshoot.

I left that for the CC to myself.

I'll take a look later.

--
--
kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

Yes....

Tell you what, if I had the state of mind that you have at the moment..... and I do and I have... that sort of thing would stress me out as well.

Obviously the clever people around here will tell you how to reduce your circuit to a purely linear one and then let you know how to look at the thing that is worrying you and also show how it should not really.

DNA

Reply to
Genome

Not exactly. This will guarantee stability, but it is not a necessary condition for stability.

The fundermental idea to stability is is there a pole in the right hand plane. That is for:

Av(s) = ()()().../()()()...

where () are 1+k.S terms, k different for each pole. e.g. (1+RC.S) terms

All small signal stability analysis is an attempt to find out where the demominater goes to zero for a particular value of S. If it does, the system is unstable. The basic isue is that finding the roots equatons is difficult. The demominator of a system is usually express as a power series, not in factored form.

Nyquist plots and bode plotes are just methods to graphically try and determine where the roots of the denominator of the loop gain is.

For Nyquist plots, "it can be shown" that the number of net encirclements of the -1 point tells you whether or not there is a pole. The summary is that stability effectivly only depends on the gain and phase at the last zero x-ing point. This means that intermediate frequencies can have gain and positive feedback and still be stable. If the phase does go to net 0 deg (180 in NF systems) then the system is "conditionally" stable. That is, it is conditioned on the gain. If the gain were to fall, the system could go unstable, e.g. vacuum tubes when warming up. Note that in RF, conditionally stable might well mean stable independent of load and source impedances, which is a different meaning.

Yes and no. RHZ cause extra phase shift, but as far as the analysis is concerned, its all in the wash. You need to to transient sims because real systems are always non-linear.

Kevin Aylward B.Sc. snipped-for-privacy@anasoft.co.uk

formatting link
SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

"There are none more ignorant and useless,than they that seek answers on their knees, with their eyes closed"

Reply to
Kevin Aylward

In message , dated Sun,

13 Aug 2006, Kevin Aylward writes

Slip there, Kevin. That's 'unconditionally stable'.

--
OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk
2006 is YMMVI- Your mileage may vary immensely.

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK
Reply to
John Woodgate

No, he just needs to "go back to school" and take a few courses in control theory.

--
 JosephKK
 Gegen dummheit kampfen die Gotter Selbst, vergebens.  
  --Schiller
Reply to
joseph2k

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.