Hi:
I have a PLL loop which works. But I sit here looking at my LTspice AC analysis schematic and try to trace signals around it from the reference phase source into the PFD, to the feedback phase from the VCO (a motor in this case) and it's just so confusing.
At DC, the thing has positive feedback! That is, due to the action of the phase error integrator (a 2nd order PLL), as well as the integration of frequency->phase which occurs in the VCO, a low frequency up wiggle into the + input of the PFD comes back from the motor as a down wiggle. But that goes into the - input of the PFD. So that would cause more up-ness at the output of the PFD than what arose from the original up wiggle that started the whole thingy.
That means it has positive feedback.
Only at the unity gain frequency of the open loop (f0) does it have negative feedback, and even then only with about 55 degrees of margin.
That is what is so counter-intuitive. A loop can have positive feedback at a frequency where gain is very high, and yet be stable as long as at f0 it's phase is just not too close to positive feedback. In fact, with
55 degrees of margin, it's close to positive feedback than negative.Then this is even more funny: A loop can be stable with 90 degrees phase. What is that? Half way to negative feedback, or halfway to positive feedback?
Ugh!