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Anti Aliasing Filter

It's the first time that i use anti aliasing filter, so i have some doubts:

1)My signal has infinite frequencies, but greater frequencies have lower harmonics.Is it correct to put fs/2 (fs=sampling frequency of ADC) at frequencies where dynamic range of fitered signal is equal or greater than dr of adc? In this way, i can use frequencies lower than frequencies where filter attenuation is equal or greater than dr of adc. 2)About noise,what should i consider?I want that noise, at frequencies greater than fs/2, has Vpp lower than lsb. But (if noise has gaussian distribution) Vpp=6.6Vrms: in what frequency range i should calculate Vrms? 3)About slew rate, i have found this link
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but i don't understand how slew rate is calculated....how can i obtain SR from SR=dV/dt|max? Thanks for the help and for any suggestion
Reply to
doc.bullwinkle
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Usually the speed of the ADC is set by considerations other than the filter's parameters and then the filter is designed to do what is required. The "what is required" part of that depends a lot on the application.

This part gets very tricky. If you imagine the desired signal not being there then the RMS is the standard deviation of the signal. This doesn't really tell you much about individual samples. When the RMS goes below 1/sqrt(12) of the LSB, it starts to disappear into the quantization noise.

You need to consider what exactly you require of the digitized signal. The aliasing folds the spectrum over so that the frequencies in the result are falling as the frequencies of the input are rising. This means that the fall off of the filter appears as a bias towards more noise at high frequencies.

You usually don't calculate the slew rate. It is usually a consideration of the op-amps in the filter. You need to select op- amps that won't distort the signal and noise that they are processing.

Reply to
MooseFET

The choice of sampling rate, the desired signal to receive, the complexity of the analog-side filter, and the complexity of the digital signal processing all interact -- so this isn't an easy question to answer. You're on the right track, though.

That depends on your noise source. In many high bit count SAR ADCs there's a broadband noise process in the chip's frontend itself that puts a lower bound on the noise voltage, regardless of the sampling rate. The only way to dodge that noise is to sample faster than you otherwise need to and filter on the digital side.

Your total slew rate will probably be close to your maximum one -- a better measure with stochastic signals or noise would be to find the power spectral density of the voltage, from which you can calculate the slew rate (with difficulty). A bit of simulation may not be a bad way to go here, or a simplified analysis that finds the worse bit of spectrum.

Questions 1 and 2 are best answered by "understand the sampling process and do some math". Try this, and see if it helps:

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Good luck.

--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html
Reply to
Tim Wescott

Thanks for the infos, i have another question...i have some problems to calculate the right opamp's slew rate to obtain right adc accuracy. I have chosen as adc AD7819

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i don't understand very well its datasheet

1)acquisition time: is it equal to sampling capacitor charge time plus settling time?Is it fixed to 100ns? 2)In the settling time associated to sampling circuit, which effect are considered? 3)If adc's analog input is connected to opamp's output, what is its slew rate? In datasheet, Tcharge became significant with R2 (input impedance) equal to 2K: in this case Tcharge shoud be equal to 56ns. So, if input is equal to Vref, opamp should have Vref/56ns as slew rate....is this right? 4)last question: at the beginning of sampling process, sampling capacitor voltage is equal to Vdd/3?If so, why equivalent sampling circuit (datasheet, figure 6) has C1 connected to ground? Thanks for the help
Reply to
doc.bullwinkle

It depends a lot on how the sample and hold circuit is done. As the internal switch turns off, there is a span of time over which changes in the input voltage will effect the held voltage.

The simplest answer here is "all of them". Many years back, I worked on a design where the power supply current changed when the sample and hold was tripped. This caused a change in the supply voltage. The change in power supply voltage effected things via the power supply rejection ratio of an op-amp. We had to consider how much to lower the supply impedance to bring this under one LSB of the converter.

The ADC is likely to contain its own internal buffer. If it does, the slew rate is the slower of the two. If not, the op-amps slew rate when working in to that much load should dominate.

No, the slew rate of an op-amp is only the case for the output moving due to the inputs changing. It doesn't consider the effects of the loading. You need to check the op-amp's bandwidth and open loop output impedance.

Reply to
MooseFET

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