About PLL

ents...

nges

Hz.

What you probably ought to be using is a PID loop, with the proportional an d derivative terms turned right down as soon as you get close to lock. Then the integral term can keep the VCO spot on the desired frequency with a ve ry low control bandwidth, just enough to beat the local temperature fluctua tions.

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Bill Sloman, Sydney

The spur sidebands on a modern frac N pll can be made very low. Or you can use an integer N pll if you prefer. If you are using a "frequency detector" instead of a phase detector, then technically you did not build a PLL but rather a frequency locked loop.

If you are happy with the results of a FLL but were unhappy with the PLL, then I suspect that the PLL was not working as well as it could.

Mark

On a sunny day (Thu, 6 Nov 2014 12:06:54 -0800 (PST)) it happened Bill Sloman wrote in :

I tried that integral thing, but there is no advantage,

First, with an external prescaler of 256 an internal prescaler of 4, the resolution is 1024 Hz, IF you measure 1 second. So having teh integral (say for example) part add one charge pulse (I tried the 4046 at

1575420000 / 256) = 6153984.375 Hz) phase comparator 2 with several 'loop filter design' software, and the result was this nervous 'too low' - 'too high' back and forward. Of course PC2 of the 4046 is typical for that. So I also tried PC2, and on the HC4046 PC3, but those easily lock on the wrong frequency. Since the frequency counter is already there, it was easy to add some PWM and some math, You can think about this:

VCO - /256 - [PIC /4 16 bits counter ] - software (fset - fmeasured) / 14000 -> 10 bits PWM ->

-> 470k --- 47k--< preset DC voltage (25 turn pot) | |-----220k--------------------> VCO | | | === === 8k2 | | 1u | /// | === /// --- 10u | /// The VCO is 22 MHz / volt, range 0-5V, gives about 100 MHz range The PWM is 0-5 V, 1024 steps makes 4.9 mV per step. Attenuated (for DC) 10 x by the 470k versus 47k makes .49 mV per step (so resolution of system). That is (.49 / 5000) * 100 MHz = 9.8 kHz per PWM step. (this is about ((1/1024)* 100000000) / 10 = 9765.625 Hz And here is the thing, you could flip very fast in priciple between two steps, to get any value in between (as DC control), but that would only cause frequent frequency changes and constellation rotation in QAM. You WOULD be (with a lot of lowpass, a LOT of lowpass) exactly on frequency. But I do not NEED to be 'exactly' on frequency, a few kHz is OK. If you reference a 10 MHz crystal (like I do) the multiplier is for 3 ppm error:

1575420000 / 10000000 = 157.542 000003 * 10000000 * 157.542 = 4726.2 Hz. So already almost 5 kHz off anyways! Whats the point?

I could be wrong (its late math.. you know), but now after a whole day running it seems to work out exactly. And perfect transmission at that, I compared te hconstellation nosie to vox (received from geostat) and Vox was much worse. But OK that is 40000 km, and the LNB oscillatro nosie added. Actually I was pissed with the Analog Devices PLL software calculation program for their ADF4360-1 2.4GHz that would or perhaps could be used, but those are so small I cannot see them anyways, I am open to better suggestions though, I have a nice 2.4 GHz VCO that I now need to solder in, but then I will also need to make a 2.4 GHz to 1.5... GHz receiver converter. But.. I have to 2016 before that sat is up. Ahead of schedule.

No. You think about using P1 which is a classical exclusive-OR phase detector, or the PC2 on the 74HCT9046 which has added overlap so that it doesn't have a dead-spot around lock

Your "nervous 'too low' - 'too high' back and forward" reflects the well-known dead-spot defect of the 4046 P2 phase detector.

--
Bill Sloman, Sydney

On a sunny day (Thu, 6 Nov 2014 13:05:58 -0800 (PST)) it happened snipped-for-privacy@yahoo.com wrote in :

The problem was that in the last experiment I used the output from the Raspberry Pi PLL as reference in the PLL (with 4046 phase comparators). The Raspberry has a fractional divider down from 500 MHz, You can set any output frequency you like, but it will for most frequencies wobble horribly with on average the right frequency. The wobble can be in the really low frequency range, where the PLL filter can not get rid of it. As I mentioned the Analog Devices ADF4360-1 has a better fractional divider PLL, but their PLL calculating software I have not been able to get running (seems to be made by some other company, was encrypted, misses DLLs in Linux wine.. All that for what should be 100 lines of C command line code). And that chip is in a way to small package. Their evaluation board is 120 $, so this was cheaper and gets the job done, more fun too. And probably better for the intended purpose. And faster... Nothing to order. There are other ways, I am just experimenting. You can for example also make an exact divider, order some exact frequency crystal 6,153,984 Hz for example, and VCO that crystal a bit with varicaps or something, I did something like that to tune the FPGA 25 Mhz crystal oscillator to the Rubidium reference, and then made the fractional divider in FPGA for my GPS pseudo satellite:

There are a thousand ways to skin a cat, I like to experiment.

I think the question one should ask is always: 'What exactly is needed?' Not: How can I break the latest accuracy record? If I break it accidently fine...

On a sunny day (Thu, 6 Nov 2014 14:16:03 -0800 (PST)) it happened Bill Sloman wrote in :

That is P3.

The CD4046 had no P3 AFAIK.

Actually it isn't. Why don't you at the datasheet at the url I posted - and you've snipped - which only shows two phase detectors , PC1 and PC2.

You know less than you should.

P2 and P3 are different output arrangements of the same edge-triggered phase/frequency detector network. Both suffer from the same problem - a dead spot around the 180 degree phase shift point.

You can get around the dead spot by biassing the system so that it locks on a point that doesn't coincide with the dead spot - as Phil Hobbs pointed out years ago. The 74HCT9046 offers a more elegant solution, but it costs a bit more.

--
Bill Sloman, Sydney

On a sunny day (Fri, 7 Nov 2014 04:12:28 -0800 (PST)) it happened Bill Sloman wrote in :

It did not, the joke is on you. The CD4046 had a zener on that pin.

I did overlook you wrote 9046, yes I know about that chip.

This is NOT about that 'dead spot', see my other reply to a knowledgable person.

In fact I deliberately created a dead band where the integral part stops by doing integer division.

I'm afraid that you are the joke.

The url to the 74HCT4046 data sheet which I posted does show a P3 output.

The CD4046 was introduced by RCA when I'd just started as an electronic engineer. This is sci.electronics.design, not sci.electronics.antiques

I not only wrote 74HCT90465, but posted a url for the data sheet.

Granting your obvious weakness in attending to detail, I doubt if you have a clue where your "nervous 'too low' - 'too high' back and forward" phase shifts come from.

Which probably wasn't either either necessary or clever.

--
Bill Sloman, Sydney

On a sunny day (Fri, 7 Nov 2014 06:27:40 -0800 (PST)) it happened Bill Sloman wrote in :

Really Slo, you should take up a soldering iron some day. It seems the last time was around that time of the CD4046. You live in the past, and have no hands on experience with any present stuff, other than babble. So in a way I see you as the antique here, most babble goes about what you did when still wearing diapers, or around that time in college or your first effort to put something on paper anyways.

Its probably not your fault, the system supports this. Nature is full of cases like that.

Nature knows what its doing,

As far as I know your neurons locked on baxandal, and that was it.

I do not expect any change in that configuration in the rest of your lifetime, but nature is full of surprises. Where there is life there is hope, but is there?

I would have expected with non-lead solder the soldering to become lighter for you :-)

Added 2.4 GHz VCO:

It is far away on the board from the QAM modulator, bit of coax helps:

The cup contains coffee. The little green inductors are decoupling from supply spikes for the VCOs, the one on the right is de-soldered, I noticed that even the capacity between two of these round solder pads is enough to get 1.5 GHz or higher through, so absolutely need to disable not used VCOs.

Now running free running frequency drift test:

Measured VCO range, will work out linearity later. I opened up this little VCO as a PCB solder pad side broke off. Not very good soldering inside, very small 2 turn coil inside, some transistors, some PCB track inductor, forgot to take a picture. Ebay VCO, so far happy with those (have several of different frequencies), date code says week 44 1997.

Time to think about a down-converter, or maybe the DVB-S card IF range is bigger than specicified... That would be cool, need to test that. Universal LNB: Rx IF LO

10700 - 11700 950 - 1950 9750 11700 - 12750 1100 - 2150 10600

2150 versus 2400 ????

12750 - 2150 = 10600 2450 + 10600 = 13050.0 lemme try to enter that 13050.0 in the sat receiver. Wow, no kernel error message from driver... Value is accepted... Have to test later if it actualy receives anything.

It's what's ON the cup that I find disturbing!

Jan and Bill settle down

Jan,

I give you a lot of credit for grabbing the bull by the horns and actually building stuff. I think it is great.

But it causes mis understandings when you try to generalize your observatio ns in your posts. For example, not all frac N PLLs suffer from phase jitte r. The one you built perhaps does not work well and your solution to find another way to create your LO instead of fixing the Frac N is fine. But i t is misleading to generalize that the frac N technique is uworkable as you r post suggested. It is very workable and if designed properly can achive performance that cannot be achieved with other methods.

I encourage you to keep at it.

Mark

On a sunny day (Fri, 07 Nov 2014 11:23:59 -0500) it happened JW wrote in :

I have more like that:

Those are very nice things.

On a sunny day (Fri, 7 Nov 2014 08:52:37 -0800 (PST)) it happened snipped-for-privacy@yahoo.com wrote in :

I did not build any, re-read my posting, I was using the Raspberry fractional PLL as referenc, maybe I did not make that clear. And that is not the fault of Broadcom either, they made it for audio, not for MHz work.

Well performance in _some_ areas.

oman

.

engineer. This is sci.electronics.design, not

My wife would kill me if I did it today. The process of expanding into the flat next door is proceeding slowly, and I've not yet got a work-bench surf ace which would survive droplets of hot solder. We rented the extra space f rom the beginning of August, but it took us a couple of months to get it re painted and to buy the bigger bed - which it's larger bedroom could accommo date - and start sleeping there. We've now moved my wife's statue of Vondel in there (and put it in my great-grandfather's glass-fronted book case) bu t getting me sacrificial table to use as a work-surface is going to take a bit longer.

I last got paid for wielding a soldering iron in May 2003. I was soldering stuff together for my low-distortion sine wave oscillator in Nijmegen in Oc tober 2012, but while I've still got the controlled temperature soldering i ron, and the rosin-cored solder, I currently lack a place to use it.

uff, other than babble.

Dream on.

u did when still wearing diapers,

That would have stopped in 1943 sometime before the CD4046 hit the market.

aper anyways.

My most recent publication came out in 2011

Sloman A. W. "Comment on 'A versatile thermoelectric temperature controller with 10 mK reproducibility and 100 mK absolute accuracy' [Rev. Sci. Instru m. 80, 126107 (2009)] ", Review of Scientific Instruments 82, 27101 - 02710

1-2 (2011).

It didn't need any soldering. It was preceded by a short thread here which you might have read if you knew about stuff like thermistors.

"Upper limit on power dissipation in NTC thermistors makes it to Rev Sci In strum" 14/02/2011

I doubt if you actually read "Nature".

The "nature" in this sense is the Shakespearean "natural" meaning an uneduc ated yokel, making mistakes he could have avoided if he knew more about wha t he was doing.

Sloman A.W., Buggs P., Molloy J., and Stewart D. "A microcontroller-based d river to stabilise the temperature of an optical stage to 1mK in the range

4C to 38C, using a Peltier heat pump and a thermistor sensor" Measurement S cience and Technology, 7 1653-64 (1996)

doesn't contain a single reference to Baxandall. It might have done if we'd gone for a Pt100 resistance sensor.

time,

Granting your disconnection from reality, you probably get surprised more o ften than most.

r for you :-)

Your expectations could be the basis for comedy program if they were less o bvious. There the fact that they are mostly totally - often comically - wro ng wouldn't be a disadvantage in that context. The lack of originality wou ld be a bigger problem.

--
Bill Sloman, Sydney

Jan,

I just sat through a seminar at a conference on PLLs for high performance, narrowband, microwave ham radio. For that we need low phase noise, quiet PLLs.

One of the tricks is to build a network to inject a small pulse to perturb the loop to manually optimize the filter to avoid hunting near the phase detector zero.

He went over how to avoid this in great deal, including spreadsheets on the loop filters, how to model it in Spice, and how to do the measurements to optimize the loop.

I'll see if I can get permission to post the presentation.

For Ham radio at 10 Ghz and up, we typically use SSB on a very precise carrier, multiplied up from 106 Mhz crystal oscillators. Any added phase noise rapidly degrades the signal to noise ratio at the distant receiver.

When your shooting for 500 to 900 mile 10 Ghz distance records, that carrier needs to be precise. So the optimization techniques are a little different then in commercial phase locked loops.

Contrast that to commercial service where the 11 Ghz band is used for 30 mile tower to tower hops.

Steve

I should add to the above post that the techniques go so far as to phase lock the 106 Mhz crystal oscillator to a GPS or Rubidium based 10 Mhz reference. So these guys really know their PLLs.

Steve R.

On a sunny day (Sat, 8 Nov 2014 06:40:05 -0800 (PST)) it happened " snipped-for-privacy@response.com" wrote in :

That would be nice, for some other project I have phase locked my FPGA to the rubidium reference, then used the internal multiplier to go to 200 MHz, then a fractional divider to all the other frequencies I needed.

SSB via the Qatar satellite would be nice, but on SSB you need to be within a few Hz not to sound like a duck, so I am curious how they do that. That requires really extreme precision on 10 GHz (down link), in such a case digital has many advantages. I can get a LNB with crystal based PLL for the LO, I think if you replace that crystal with some reference locked to say rubidium it would improve things. I have to modify a LNB anyway for this, that project is on the table too.

I tried today to receive out of band 2.4 GHz with 2 different DVB-S receivers via the IF input (LNB input), those have IF range of 950 to 2150 MHz, but that does not work, 2.4 GHz is too far out of band it seems. One gives a kernel error message (Cinergy S2 USB HD), and the other no error message (Hauppauge wintv nova PCI), but no signal either. So I designed (on paper) a small down converter 2.4 GHz to 1.5 GHz or there about (VCO), and collected parts, found a box (plastic!!), and a voltage regulator. So next is to solder it together and test it. Plastic box, that HD receiver is also in a plastic box... very stable. :-) For this DVB-S project in retrospect I should have used FPGA from the beginning.