Hi guys, I am looking at a circuit which involves multiple supply voltages (+5V,+9V,-9V). This is a proof of concept. And it involves RF also. Since it involves RF, I am thinking of making power supply board separate from RF section in the proof of concept. Is it advisable to keep +9V and -9V on a separate board and the +5V in another board. The power requirement is upwards of 300 milliamps. In that case the ground will be spread out in two different boards. The 'noise' factor comes into play . And we have to take care of impedance matching also. So how do I go about it. Your valuable suggestions are invited.
The usual approach is to use a multi-layer board and bury the power planes (and possibly a ground plane or two) on the inner layers. If your radio-frequency is high enough that you have to lay out the active section of the board as transmission lines over a continuous ground or power plane you have to be careful to put ther right power plane directly under the controlled impedance tracks, so that the signal current in the track is reflected (and - as a source of radiated interference - largely cancelled) by the return current in the power plane directly underneath it.
Hello Sir, What do you mean by active section. s it the RF section. My system also involves IF as you may be knowing. And do I have to use a powr plane , next a ground plane next a power plane etc. ie Do i have to sandwich power and ground planes.
************************************************************ "you have to be careful to put ther right power plane directly under the controlled impedance tracks"
************************************************************* I did'nt understand this. Could you elaborate on this?
What do I have to do to minimize reflection. Is it just impedance matching or do I have to take any external factors into consideration?
Your local oscillator will presumably be pretty closer to 900MHz too and the signal(s) going from it to your mixer/demodulator will presumably also be routed along impedance matched transmission lines.
The intermediate frequency output from the demodulator/mixer will presumably have very little high frequency content and can be routed with less attention to detail.
etc.
No. You get free plane-to-plane capacitance if you do, but not enough to get excited about.
The painful experience that impressed this on my mind was on a boad where we were tracking 800MHz clocks and 1.25nsec wide carry- propagation pulses; the signal were all ECL level (though in fact were were using Gigabit Logic's GaAs 10G Picologic parts) and each track should have been routed over a buried -2V plane.
Each of these tracks was terminated by a narrow 50R surface mount resistor that connected directly to the -2V plane. Each voltage transistion propagating along a track accompanies a pulse of current that charges up the track to power plane capacitance, which was obviously coupled to an equal pulse of current (in the opposite direction) in the power plane under the track. When the current pulse in the track hit the terminating resistor and propagated down into the power plane, it cancelled out the complementary current pulse in the power plane.
The prototype printed circuit was built with the inner layers in the wrong order - the printed circuit department "knew" that the order of the innner planes didn't matter, and changed the order to make the structure more symmetrical.
The -2V plane was no longer the "ground plane" under the track, and the current flowing through the terminating resistor had to follow a long and tolerably inductive path to the power plane where the return current had actually been flowing. We got a lot of reflection.
We ended up replacing the critical tracks with minature (1.2mm diameter) coaxial cable.
It's just impedance matching, but you have to be careful about the actual impedance of the current path from the track through the terminating resistor to the "ground" plane under the track.
In one application, where I was driving a couple of ECLinPS flip-flops from a common 200MHz clock, I narrowed the clock track in the vicinity of the tap from 50R to 75R for about a cm or so to compensate for the capacitance of the flip-flops clock input. This was almost certainly over-kill, but I was practicing for the 500MHz clock frequencies that should have come up in the follow-on development.
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