high-Z
relating
Obviously - although a read when the port is set to OUTPUT will read back the contents of the register as last written. This doesn't read the pins' status of course.
The control register in a properly functioning mobo's LPT port should act like any other register, holding the contents of the most recent byte-write. If it doesn't, IMHO it is stuffed.
How long the instruction "lasts" is not a relevant point. A write to a register is a write to a register. If the reg is functioning properly, the write "sticks". There is no "hardware timeout" on the register I/O.
You don't need assembler to check what is happening - you can read the control register in (Q)Basic. If C5 doesn't match what you last wrote, there is a malfunction. But do allow a finite time between port direction changes and read/write attempts. I had one project stalled for over a year looking for an external hardware issue because I was changing C5 0->1 and then writing a byte, which was not being read properly by the attached device. A short delay loop between setting C5=1 and writing the byte solved the problem (QB4.5, P1-133 and P3-666).
As per the description above, if it isn't behaving as I described then I would be getting another mobo.