Anyone have any ideas as to why the IC mentioned above might be so sensitive to static shock? I've been through nearly a dozen, and they all end up blown in the same fashion. Seem to function, but the Q and Not-Q are somehow seperated such that Q seems to act like +5V and Not-Q acts like -5V. I am using the two to bias a transistor for testing, and the results are always the same. One will properly bias an NPN transistor and the other will proberly bias a PNP, but the two don't meet in the middle. Both must be connected to the circuit for it to function. But in my first prototype, only Q needed to be connected for both types. Not Q was left unconnected without ramifications. And static is the only apparent variable. When handling the ICs at a static-safe workstation with nylon tweezers, all goes well. but any exposure to a non-static-protected environment damages the chip in this fashion, and only in this fashion. I am guessing a very sensitive gate, or one constructed in a less than robust fashion. Eager to hear what others might think. And getting tired of having to be so meticulously carefull...
Dave