Question on CD4027BE dual J-K flip-flop...

Working with the above mentioned part, and am beginning to wonder about something I *assumed* (hate that word) to be the case. If Q and not-Q are compelmentary states, this would be logic 1 and logic 0, right? Or is it

+5V and -5V? I just figured it would be logic 1 and ground, but the way my circuit seems to operate makes me wonder. Any commments are more than welcome. (Don?) I guess I could drag out the scope, but would love to hear something from those in the know as to how it *should* be.

Thanks,

Dave

Reply to
Dave
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Hmmm, not enough information to make an educated guess.

According to the data sheet Maximum Value of DC Supply Vdd to Vss is

+20V max.

What it should be is that ever is connected to pins 16 Vdd and pin 8 Vss.

A schematic would help to not guess, but with the limited information you gave, what did you expect ??

don

Reply to
don

Yes, unless you're asserting both Preset and Clear, in which case the outputs will be the same (defined by the part).

It is whatever logic 1 and logic 0 is defined to be and the way the component is connected, (usually Vcc/Vdd and ground).

"Logic 1 and ground" makes no sense. "Logic 1" is whatever level you define to be "logic 1". Ground is a voltage and independent of the logic level assigned to it.

Most often, Logic 1 is defined to be your positive voltage (in this case 5V) and logic 0 to be ground. You can define them the other way, if it suits your purposes. It is unlikely that '1' is +5V and '0' is '5V, but it is certainly possible if your FF is wired from +5V to -5V.

Reply to
krw

Yeah, sorry. Guess I didn't provide much info. Apologies. Obvious newbie here.

Let me try to post a schematic to abse and see if I can correct the situation. Do appreciate your patience.

Dave

Reply to
Dave

Just posted the schematic and a description of its supposed operation to abse. Please fire away with any questions, criticism, whatever.

Thanks,

Dave

Reply to
Dave

Assuming "true" logic, logic 1 is Vdd (or Vcc as it's sometimes called.) Logic 0 is ground.

Vdd is, electrically, whatever voltage you decide to use. Might be +5, might be something else.

John

Reply to
John Larkin

Hey John,

Please see my post on alt.binaries.schematics.electronic. It contains the (cleaned up) schematic and the problem I am trying to address at this time.

Thanks,

Dave

Reply to
Dave

Thanks for the schematic.

As I stated previous, the outputs will be whatever is connected to Vdd and Vss. Your schematic has +5/GND so the outputs can not be anything but those values.

I also see that the -5V supply is connected to only pin 7 on the

74HC5043. ( which is the Vee pin)

-5V will never by output from the 74HC5043 unless there is a -5V input.

This schematic requires me to "wire up" the missing connections from the

74HC5043 to the transistor socket.

Thats your job, please correct this schematic and re-post.

don

Reply to
don

Yes, I realized this along the way. sigh. But I am still left wondering why I have to fiddle with Q2 and not-Q2 to get full functionality.

Yeah, I'm working on that. Felt I ought to post what I had so far, and try not to make anyone wait for days and days before they saw *anything*, just in case the answer was something so obvious I could be the only one missing it. Will rework and repost. Thanks for your patience.

Dave

Reply to
Dave

Just posted the reworked schematic to abse.

Thanks again,

Dave

Reply to
Dave

If you're powering your chip from 5V, yes, Q & -Q should be either 5V or

0V. Also, Q & -Q are, by definition always at opposite states.
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Reply to
Bob Larter

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