Notches in ground planes for multi-power multi-channel board

Yes. Add some big electrolytics in parallel to C22 and C29, the required capacitance depending on how many cycles of quiet time you need and how much each rail pulls. You may have to add current limiting to the input where Q91/Q92 are. Else charging up the big electrolytics at power-up could take a toll there.

But I wouldn't worry too much about noise if you do a good layout. On ECG units we never stop the clock.

Absolutely. It's good that you have the resources available to do that.

Looks a little complex, especially if you can shut down the switching during digitizing.

John

"

I guess it may make more sense to synchronize the switching with the ADC sampling (200kHz ADC) since both of these interfaces come from the FPGA.

As long as the common mode/switching noise doesn't last more than a microsecond or so around each switch point. I wonder if a common mode choke would exacerbate this problem, may be better to use no common mode filtering if the switching is synchronized?

cheers, Jamie

"

look up symmetric PWM - rather than a sawtooth, it uses an equilateral triangle. this is done all the time in 3-phase PWM (AKA Space Vector Modulation). The peak & trough of the triangle waveform *always* correspond to the exact center of the high & low pulses. Syncing the ADC S/H thusly means the sample is always as far as possible from the switching edges.

and when trying to make, say, sinusoids (its also true for DC) you will notice that the centre of the pulse is equal to the desired output current - so sampling like this automagically removes the switching ripple artefacts.

Cheers Terry