Not attaining required slew rate on differential ADC input buffer

Oh yes - and just to note that the buried AGND plane is unsplit. There are no other traces being routed in this layer. There's no space for a single AGND plane on the *top* side of the PCB.

Nicholas

I would try using a different part to do the single ended conversion. What could be happening is that the gain bandwidth of the part decreases when one of the op-amps gets near its limit.

The circuit appears to be a bad one. In general you don't want to do anything that raises the impedance that the ADC sees. ADCs tend to have funny spiky currents on their inputs. You don't want the buffer to react badly to these but you also don't want the voltage at the inputs to change. I would only use very small values of R. The capacitor should only be big enough to make the impedance that the converter sees remain low as you go beyond the gain bandwidth of the op-amp.

Good stuff, Ken. I'll have to play around with RC values, keeping R as low as possible.

Thank you for your response!

After a bit of experimentation, I've finally found the problem causing distortion on the op-amp outputs. To me, the issue was not immediately apparent.

(1) The ADA4941-1 op-amp has a disable pin. It appears that this pin does not completely disable the output. Rather, I've found that when the disable pin is connected to a voltage level significantly higher than the negative voltage rail, there will be distortion on the output.

IMHO, it is best to leave this pin floating if it cannot be guaranteed that the disable pin is connected directly to the negative voltage rail. It appears that there is already a pull-down resistor on this pin which is located inside the device. Further information can be found in the datasheet regarding voltage thresholds for this disable pin.

(2) In addition, 0.1uF caps on the Voffset1 and Voffset2 nodes do not cause distortion on the output when the disable pin is left floating and the device is not disabled.

(3) As suggested in this thread, the 2.7nF caps situated on the outputs may be too high, and will limit the slew rate. I have not found optimal capacitance values yet, but I will have to do some additional experimentation.

Many thanks for your help, John and Ken!

Nicholas

For the RC filter, I chose values of R = 91 ohms, and C = 220pF.

Nicholas