So you have no interest in diodes, resistors, capacitors, or inductors. And no interest in the C-V behavior of ESD diodes.
Fine by me.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
Because passivation is a rel issue and not an electrical spec, nobody really tells you their foo. The only thing you can do is pay one of the valley materials labs and they will figure it out. But CVD variants are common, as is the silane process you mentioned.
But after the wafer is diced, the side is now exposed. That is where more foo comes in. There is all sorts of foo in the scribe to keep (so they say) contaminants out. The scribe rules are proprietary in theory to the factory, but they can't be kept very secret since layout needs to know them, and of course the mask shop will know how you do your scribe. These rules are as secure as a NDA.
I used to work at IBM Research, where an enormous amount of the basic science and development for both advanced bipolar and CMOS was done. (In fact, I had a fairly major HF leak from the fab upstairs into the core behind my lab at one point.)
When I branched out into silicon photonics a dozen or so years ago, I did my own process development, including writing dozens of my own run sheets for up to 300 process steps, front end and back end. So I know a lot of the details without needing an NDA, though I'm nobody's idea of a CMOS expert.
It's amazing what you can get done when you can walk down the hall and bug the world's expert on some topic. I used to share the back wall of my office with Bob Dennard, the inventor of DRAM among many other things, and there were others like him in many other fields.
Of course now there's a lot more software done there than hardware, but it was a great place to work back in the day.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
There was water set free when melting the glass of those CERDIP packages ( the ones made from top & bottom ceramic with a glass layer in between where pins came out) Often seen on Eproms.
There was no problem with the sidebrazed ceramic packages.
It is amazing at what they don't tell you at places where you are employed. If you don't need to know it, the fab will not tell you. [IBM wafer fabrication isn't exactly like the dog eat dog world of commercial semiconductors.] There are a number of latch-up prevention schemes I stumbled across having material companies do analysis. Probably the only one safe to reveal was one company that used to ion implant their wafers from the back to make what amounted to a low resistivity layer, like a faux epi wafer. This was easy to find since the sheet rho measured didn't match the published value. [The published value was at the surface of the wafer.] Since everyone uses real epi these days, there is no harm in revealing that one. Some companies use beta killing schemes, which could still be in use.
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