Never Buy Maxim (again)

What "C-V behavior" are you referring to? ...Jim Thompson

So you don't know what you measure under power-down conditions either? ...Jim Thompson

OK, which one is worse?

Clueless.

Well, with one you see what you're getting. The other, you don't.

You are? ...Jim Thompson

Ignore him. He hasn't made sense in years.

The input capacitance of an op amp, or really any input pin, is a combination of stray capacitance to a field and junction capacitance. [The stray capacitance to a field is a combination of capacitance in the package, bonding wire, and interconnect over substrate.] It makes no sense to measure the capacitance unless the junctions are properly biased. Seriously, this is component eval 101.

Not only do you insure the device is powered up properly, but you need to insure the the SMU will not force the input out of normal operation. And of course there is the issue of nulling the test fixture capacitance. Low level measurement is a skill.

It is pretty rare a chip is at fault. When the dust settles, it is nearly always pilot error. That is why eval boards are sold. Think about it. The unit is in production. Even a loser product will sell a few hundred thousand units a year, so why does it work for everyone else but not you? Pilot error.

You might want to consider how sample stock at a semi is maintained. When the part is deemed sellable, tested units from that lot are put into the sample stock. Over the years, the sample stock can be pretty old. Now if there is an electrical specification change in the datasheet, the sample stock will be pulled and retested. But otherwise, the sample stock is from the very first batch. Now it will meet the electrical specification, but it could possibly be different in some manner not tested. Processes shift, wafer vendors change, etc. It is an analog world. This variance shouldn't be a big deal, but if you depend on some parameter that is not tested, don't expect the current production to match the sample stock.

A lot of those op amp designs were from Gain Technology. Arizona. Need I say more? Actually they had a few good engineers, but over all mostly wankers.

ESD capacitance? We are now making up specifications?

The ESD structure is part of the pin capacitance. However, nobody specifies the capacitance of the part that is not in a normal operating state.

ESD testing is a totally different ballgame. The vast majority of chips are designed to pass ESD as found in assembly, and not to withstand ESD from the outside world. Read the data sheet carefully.

Note the ESD test is not done on a powered circuit. Remember, it is only for handling purposes. The tester can float or short the pins not under test. Generally it is more rigorous to test ESD with the power supply pins floating and the remaining pins grounded. That forces two ESD structures to turn on.

ESD is tested two way. One is a characterization test. The ESD tester is hooked up and a curve tracer is attached to the pin. You examine the VI characteristics of the pin after each zap. You increase the voltage until it obviously fails. After noting at what voltage it breaks, you test a fresh unit on another pin.

The other test method simply takes the QA ESD limit and zaps every pin at that limit, both positive and negative. Then the part has to pass the test program. The QA limit is pretty low, maybe 2500 to 3000v. The pins are generally above 10kV.

Somebody really ought to write up a handbook of chip QA. ESD and latch-up testing confuses a lot of customers.

CV is really a bad choice of words, but I don't think John means CV testings as in determining mosfet threshold.

Tossing out buzzwords is generally not a good idea if you don't know what they mean.

He's just throwing buzz words. He knows not of what he barfs. Are we surprised? No. ...Jim Thompson

So, if the fixture is all set up and the c-meter is connected, before power supplies are turned on, you are going to avoid looking at the c-meter? Maybe put a black towel over the meter so you can't see it?

Boonton c-meter, 20 millivolts at 100 KHz. But I was going to measure capacitance a few different other ways, using the opamp itself. The bottom line here is noise peaking, so I was going to do that, too.

The fixture, without the opamp, was 0.62 pF.

Customer support is, apparently, something that also requires skill.

Arizona? That explains a lot.

OK, I'll fill you in:

C means "Capacitance"

V means "Voltage"

Don't be tedious. ESD capacitance is the capacitance of the ESD diodes. What else would I be measuring?

So that is, apparently, something that you adamantly don't want to ever measure or know. Cover up that C-meter so you don't accidentally find out.

Some of us care about input capacitance a lot. For TIAs (photodiode or otherwise) the op amp's high frequency noise current is dominated by its input noise voltage differentiated by the total capacitance on the summing junction.

The best op amps I know about have Cin of about 1.4 pF, so something down at 0.4 pF with reasonable voltage noise would be pretty interesting for some things. For instance, I recently did a front end for a surface voltage tool, which basically holds a probe tip a couple of mils above a spinning wafer. The work function depends very strongly on surface contamination, so you can map out sub-monolayer oil slicks and such like.

Dropping the input capacitance by a whole pF would have been nice.

Cheers

Phil Hobbs

There are all kinds of CV measurements. MOSFET threshold is just one--for instance, you can get the doping density vs. depth in a diode by measuring C(V). I've learned a lot of interesting things about photodiodes that way, but it's more commonly used for incoming inspection of wafers--you use a mercury or (nowadays) gallium electrode for the top contact.

Cheers

Phil Hobbs

Sadly, I've found Maxim 'specs' to be more like "intereting goals" which some parts actually met.

Too good to be true? I take it that that was what John wanted to find out. Of course engineering is divided into two sets of axes, real space and chart space. You can do a lot of amazing things as long as you never leave chart space. ;)

Cheers

Phil Hobbs

Hi Phil, Say do you have a good reference for the C-V doping density technique.

I find a bit in Sze's book. I guess I can follow the references in there.

George H.