VDMOS nonlinear capacitance is modeled in terms of Vgd.
Too bad a real MOSFET doesn't show a steplike change in Ciss as Vgd changes sign. (This is easily demonstrated with the gate charge test circuit, watching the waveform at low Vdd. The cutoff slope depends only on Vds, not Vgd.)
So many decades of bullshit to sift through...
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
On a sunny day (Fri, 22 Sep 2017 23:21:30 -0500) it happened "Tim Williams" wrote in :
simulations are not reality, pokemon is not real.
NASA has never been on alien planets.
Not every circuit is a Baxandal
GlowBallWarming is real. Roger Rabit is fake.
Are you referring to the flat spot in fig 16?
-- John Larkin Highland Technology, Inc lunatic fringe electronics
est
ds
Isn't that why you breadboard something after simulating it - to make sure the simulation matches the real world... So many models fail the reality test.
Just ask HVAC engineers trying to model how heat flows in a building when you add in the outside world!
John :-#)#
I know, that's why I'm trying to do Crysis!
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
sure the simulation matches the real world... So many models fail the reality test.
Thing is, they could've constructed this model realistically, just by changing around a few things even. The model structure is old, probably since the 90s, and no one thought to question it for two or three decades.
This is what the goofy model does:
What they got right: Ciss changes with Vds. The slope below the Miller plateau is different from the slope above (where Vds = 0, because the transistor is shorting out the load resistor).
What they got wrong: Ciss (below Miller) is supposed to change slope. Over the whole Vgs range, from negative voltage until conduction begins. The slope is very nearly linear. (This could be the basis for a fantastic parametric amplifier.) As Vds rises, the slope rises (Ciss drops), and the Miller step gets longer. (The model does not reproduce Qg(Vdd) very well.)
The most ugly part is how the Vds=0 slope encroaches on the Vds>0 slope. At a glance, it looks like Miller step, and it's just slowing down because it's beginning to conduct, right? But no, it /can't/ start conducting that sharply, and it doesn't start conducting at all in that range (Vto = 3.6V!). It's because the model has Cdg(Vdg) instead of Cgs(Vds) and Cdg(Vds).
The real thing behaves as you would expect from the C(V) curves in the datasheet, taking them naively as the only nonlinear capacitances in the part. Well, it turns out that's not naive at all! Coss does not depend upon Vgs, and neither Ciss nor Coss depend on Vdg. Evidently, the reason they plot only the three capacitances they show, is because those are the only relationships present! I'm a bit shocked myself!
Don't you just love fields were "just-good-enough", or often times, outright bad, information persists...
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
Yes. Those are just cartoons, BTW -- no real transistor looks quite like that. The corners are rounded, and the plateau isn't horizontal (which would be silly). IXYS actually plots measurements rather than cartoons:
The model thinks it looks like this:
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
On a sunny day (Sat, 23 Sep 2017 12:57:08 -0500) it happened "Tim Williams" wrote in :
mm had to look that up:
N Korea! Well I am all with Kim ;-)
Except for the soft corners, their plateau is horizontal.
Different mosfets, made on different processes, can be expected to have different diffusion profiles and different C-V curves. Some slope very gently, some have steep drop-offs. Like different diodes have very different C-V curves. I hardly think that a bunch of mosfet makers are publishing erroneous C-V curves; they have expensive test gear.
A Spice model of transition gate and drain volts usually has a flat plateau, as the drain slews in its transition and feeds back into the gate through Crss. I don't think that decades of academic and industry Spice mosfet models are lying.
The data sheets are usually unclear about how they measure the gate charge waveforms. They specify Vd and Id, but is the drain fed by a constant-current source, or a resistor?
A little rounding of the plateau corners doesn't matter much in real life.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Fun quiz: find out how many things are wrong with this circuit:
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Inflection point != flat. The same can be said of mine,
A bunch, perhaps not. ST, definitely.
FYI, there's only one kind of diode I'm aware of, with an m that large (IIRC, even hyperabrupt varactors are only m ~ 2). The extreme dropoff (albeit not as extreme as their plot) is characteristic of the SuperJunction structure.
Here's such a diode:
Diffusion profiles have very little to do with it. The active stuff on the top of the MOSFET (epitaxy) is physically shut off from the drain terminal after maybe 20V, because of how they've shaped the source, substrate and their doping profiles, and the SuperJunction pillars. You can't make depletion that aggressive with diffusion!
So my pictures are made up?
Because someone's got it wrong. Is it the SPICE model or the oscilloscope?
IR seems to suggest CCS (as in your other post). ST uses essentially the same circuit.
IXYS doesn't say. I checked the appnotes. They don't seem to have any publications since 2003 or thereabouts, which means their appnotes don't even cover the debut of SuperJunction parts. Shame.
I think that I've seen the measurement done with a load resistor (which is what I've done). Can't find an example to confirm that right now.
In any case, the SPICE model was measured with the same method.
Reality is continuous. Seems to matter an awful lot...
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
You had a drain resistor, no? See my post below.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
On Saturday, September 23, 2017 at 6:14:09 PM UTC-7, Tim Williams wrote: ...
...
Is channel 1 the drain?
If so how come the drain is at zero volts before the Miller plateau on the gate (Ch3?)
If so there is no feedback through Cgd at that time.
thanks
kevin
Uh, so?
On a related note, ST does actually have a document showing resistor load.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
On a sunny day (Sat, 23 Sep 2017 13:10:09 -0700) it happened John Larkin wrote in :
I like it ;-)
What's wrong with it?
If you set the Vgs right for the top MOSFET, then the current is almost perfect except for the last couple of volts drain-source
Cheers
Klaus
Looks like different manufacturers use different load circuits, and most don't reveal it. That will change the shapes of the curves, but not much affect total Qg.
Fig 12?
Fig 14 includes Vd and Id, which is not usually on the gate-charge curve. Interesting things going on there.
The self-heating model, fig 1, is nice. I've done that in power amps, measured heat sink temp, fet voltage, and fet current, and run a realtime Tj simulation as the shutdown mechanism. That lets one safely push the fets a lot harder than any simple current limit. We derive our thermal models by blowing up fets.
We're doing that again now, in our SSR module, but we're protecting a wirewound resistor, not the fets. A dual RC is probably a decent model. I'm accumulating a nice collection of exploded resistors.
Not to change the subject (me?) but I'm testing a wirewound resistor this weekend, at 20J per shot. Viewed under my Mantis, every shot reveals the wire coil, under the silicone coating, by a brief red spiral-shaped flash. But with the illumination turned off, in the dark, there is nothing visible. So it's not incandescence, but a transient change in the chemistry of the coating?
-- John Larkin Highland Technology, Inc lunatic fringe electronics
On Saturday, September 23, 2017 at 12:25:24 PM UTC-7, John Larkin wrote: ...
...
The plateau will not be quite horizontal - its slope will depend upon the v oltage gain which depends upon the gm of the FET and the effective resistan ce at the drain circuit.
There has to be enough gate voltage change in the plateau region to cause t he drain voltage to change to counteract the charge being suppled by the ga te circuit to to the other end of Cgd.
The test circuits with a constant current sourcing for the drain will have the most gain, the ones using another identical device as the CC source and the ones using a resistor will have decreasing order of gain and larger ga te voltage slope on the plateau.
The one using an identical device seems a reasonable standard as the gain w ill be "gm*Ro/2".
kevin
All the capacitances are changing in real time, too.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
...
Yup, agreed
This is a curve I measured for a BSS138 at low current - there was about 160mV change in gate drive during the run down.
There is a fair amount of curvature of the drain voltage slope.
I used your technique of documenting it within the photo - good idea.
kevin
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