Is there a tidy way to model an edge triggered monostable (one shot) in ltspice.. All I can think of is using the behavioural flip flop in some fashion. afaik that's the only way..
D from BC myrealaddress(at)comic(dot)com British Columbia Canada
It looks like the cleanest way to make a quick model of it.
If you have the Q charge and RC that hits the CLR when the voltage gets to some level, you will have most of it. An ideal switch could discharge the capacitor between pulses so that history has little effect on this cycle.
LT Spice has delay lines.
John
Retriggerable or non-retriggerable? A simple one-shot can be made out of an xor gate and an R-C or a few gates.
-- Keith
So the recipe is:
1 flip flop 1 delay line (instead of an RC)Neato... D from BC myrealaddress(at)comic(dot)com British Columbia Canada
I think retriggerable.. In other words, triggers can keep the circuit output high. (Assume all digital positive logic.) Once the triggers stop, the output will zero after a time period.
Using gates sounds good too.. I guess that's about it. Gates or flip flops..
I wonder why the one-shot doesn't get it's own symbol and parameters.
D from BC myrealaddress(at)comic(dot)com British Columbia Canada
The delay line can remember more than one event. The RC only remembers the voltage on the capacitor. If you are after a normal sort of oneshot, use the RC.
Use the NE555 in the misc directory?
Cheers, John
Isn't that model full of components? If so, it'll will run slower than a primitive model. I'm just looking for function and not to simulate any real parts.
D from BC myrealaddress(at)comic(dot)com British Columbia Canada
On Mon, 10 Nov 2008 20:01:52 -0800, D from BC wrote:
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JF
oops I should have wrote that I'm looking for a short cut, not a schematic. (Was still interesting to see a NOR cct opposed to a ff cct. )
What I'm really after is a behavioral monostable model in ltspice or near equivalent so I don't have to make a monostable model with flip flops or gates.
Some monostable attributes might be: Retrig or nonretrig Ton
I wonder if an international symbol for a monostable exists...
D from BC myrealaddress(at)comic(dot)com British Columbia Canada
In article , snipped-for-privacy@comic.com says...>
Input feeds inverter and RC. Output of inverter and RC feed NOR. Positive edge causes one input to the NOR to go low (from inverter) immediately and the other to go high after RC. During the time both are low the output is high. ...or something like that.
AND/OR gates do the same as XOR, except only trigger the monostable on one edge.
Sure. I've seen several (Mustart Bible anyone?) That's the nice thing about standards; there are so many to choose from.
-- Keith
I noticed that the answers here wher,e IMHO, not ideal and not fully behavi oural. I was facing a similar problem and needed to use a monostable for ac curate timing in a gate drive application to create dead time. At these nan o sec speeds, the solutions began to break down. However I did find a solut ion. It is entirely behavioural, a little heavy on the computation, but wi ll work at all speeds and the timing does not require any RC elements. It uses the LTSpice DFlop, with the data line tied high and the clk input u sed as the positive going edge trigger. This is placed in combination with a B source to delay the output and then use this to trigger the CLR input o n the DFlop after the desired monostable period. However to achieve the tri ggering the B source should be a bit funky. Simply using the output delayed causes problems at high speed and would prevent the monostable being retri ggered until at least 2xperiod. My solution was to use a B source to take the first order derivative of the output. The derivative is computationally expensive so I mask it with a si mple IF function. This means the derivative is only computed during the tra nsitions. Care should be taken with the mask, as any settling on the DFlop ouput could cause issues.
ASDEAD_TIME_DELAY 1V 0 N001 0 DELAYED_CLR 0 OUT 0 DFLOP trise=1n tfall=
1n B1 DELAYED_CLR 0 V=IF(V(OUT) > .1,ddt(delay(V(OUT),10n)),0) V1 1V 0 1 V2 N001 0 PWL(0 0 100u 0 100.001u 1) .tran 0 2m 0 .backanno .endEnjoy Aidan
On Wednesday, October 21, 2020 at 10:17:55 PM UTC+11, Aidan Walton wrote:
vioural. I was facing a similar problem and needed to use a monostable for accurate timing in a gate drive application to create dead time. At these n ano sec speeds, the solutions began to break down. However I did find a sol ution. It is entirely behavioural, a little heavy on the computation, but w ill work at all speeds and the timing does not require any RC elements.
used as the positive going edge trigger. This is placed in combination wit h a B source to delay the output and then use this to trigger the CLR input on the DFlop after the desired monostable period. However to achieve the t riggering the B source should be a bit funky. Simply using the output delay ed causes problems at high speed and would prevent the monostable being ret riggered until at least 2xperiod.
he output. The derivative is computationally expensive so I mask it with a simple IF function. This means the derivative is only computed during the t ransitions. Care should be taken with the mask, as any settling on the DFlo p ouput could cause issues.
=1n
You can do it with simple transistor models. Here is one that I have posted here recently.
It uses two BFR92 5GHz transistors, and produces a 25nsec pulse from a rath er narrow trigger pulse.
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3 IKF=0.46227 XTB=0 BR=10.729 CJC=946.47E-15 CJE=10.416E-15 TR =1.2744E-9 TF=26.796E-12 ITF=0.0044601 VTF=0.32861 XTF=0.3817 R B=14.998 RC=0.13793 RE=0.29088 Vceo=15 Icrating=4m mfg=Infineon ) TEXT -904 1024 Left 2 !.tran 0 500n 0Bill Sloman, Sydney
A simple RC can do the d-to-clear delay. Add a diode if you need fast recovery.
A transmission line is fun for flop reset too, if you don't need high duty cycles.
You don't even need the flop: a transmission line and a gate make a one-shot.
Or an RC differentiator driving a Schmitt gate. We do all of the above in real life. And others.
-- John Larkin Highland Technology, Inc Science teaches us to doubt. Claude Bernard
avioural. I was facing a similar problem and needed to use a monostable for accurate timing in a gate drive application to create dead time. At these nano sec speeds, the solutions began to break down. However I did find a so lution. It is entirely behavioural, a little heavy on the computation, but will work at all speeds and the timing does not require any RC elements.
t used as the positive going edge trigger. This is placed in combination wi th a B source to delay the output and then use this to trigger the CLR inpu t on the DFlop after the desired monostable period. However to achieve the triggering the B source should be a bit funky. Simply using the output dela yed causes problems at high speed and would prevent the monostable being re triggered until at least 2xperiod.
the output. The derivative is computationally expensive so I mask it with a simple IF function. This means the derivative is only computed during the transitions. Care should be taken with the mask, as any settling on the DFl op ouput could cause issues.
=1n
A transmission line can be DC-coupled and terminated. High duty cycles do m ean that you do have to be picky about reflections, but source and series t ermination does help.
Delay lines are useful when you need short delays. I used one in 1976.
Sloman, A.W. and Swords, M.D. "A fast and economical gated discriminator", Journal of Physics E: Scientific Instruments, 11, 521-524 (1978).
I've even used short lengths of coax for the job, though 1nsec takes 20cm o f coax - when we wanted a 500psec wide blanking pulse, 10cm of miniature co ax turned out to be the easier way to get it back in 1983.
-- Bill Sloman, Sydney
Unlike the real world a spice sim doesn't have noise and components don't v ary. It would work perfectly well to have an input control the discharge o f a capacitor with a given RC delay driving a digital device with a specifi ed input threshold. Output can be whatever polarity you wish. I created a n oscillator for a device that used an external RC and it worked perfectly well, very stable, always started.
That sim did take a lot of simulation time though. I never tracked down wh at part of the simulation was causing that. I needed to deal with a varyin g Vcc so I had my own models for the digital parts which typically don't su pport that. LTspice is a very clumsy tool for pretty much anything digital . They just never did much with the digital parts to make them work well f or most values of "well" that suit a digital design.
-- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
I'm not aware of LTspice supporting behavioral models. What you are lookin g for is just a transistor or an OC buffer discharging a cap to ground, pul led up to Vcc and an output buffer to shape the result. Nothing fancy. Th at is retriggerable. For a non-retriggerable Change the input buffer to a gate that disables the short to ground unless the cap is charged up... opps , I just realized you need a splinter pulse since the input is edge trigger ed. So an inverter driving a short RC and an AND gate to detect the change on the input. This output is OC to momentarily short the cap to ground. Add a loop back to disable the input gate when the cap is timing.
Wouldn't know. Not much need for the things in digital design.
-- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
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