Mains voltage zero crossing detector with optical isolated output

Show us.

Sheesh, no imagination!

Dump D1 and D3 and replace R6 with a cap. The value of the cap might be interesting.

Or dump D1 and D3 and R6 and add a 180K resistor from U3-1 to +5V.

Snap-action added to satisfy Mr. Know-it-all...

Works _without_ tweaking (within 62us), but he-of-questionable-parentage will just keep on obfuscating. ...Jim Thompson

Are you _really_ that ignorant. Post your schematic so that others can laugh too.

Of course you conveniently forgetting forward-biasing the ESD.

Oh! I forgot! Those rules don't apply to you, just to those you criticize.

You are certainly an amazing little bastard ;-) ...Jim Thompson

Unless you know an even better way... which you obviously don't >:-} ...Jim Thompson

Quit smirking and try it.

I'm *using* the ESDs as clamps. Any modern HC part is good for at least 50 mA.

If you are for some reason afraid of ESD current, 1N4148s aren't a fix.

Why use an HC14, when you can just add more parts?

Only 20 parts, a couple shy of your Personal Best.

So, you've given up on insulting my wife and moved on to my parents?

so

=A0 =A0 =A0...Jim Thompson

=A0 =A0 =A0...Jim Thompson

Datasheet for hc04 says: input/ouput clamp current: +/-20mA, Continuous current through gnd or vcc: 50mA The input and output voltage ratings may be exceeded if the input and output current ratings are observed

TI datasheet from 1982, so unless they have gotten worse since then I don't see how that can be interpreted as do not forward bias the ESD

-Lasse

I can't figure out if you are just rolling or really need a drawing to put in a synchonizing flipflop and see that sampling an async signal with a flipflop is a recipe for metastability.

read all about it...

-Lasse

I know not to put slow edges into the D input of a flipflop... or into an HC04. Metastability data, if you can find it, doesn't account for slow input transitions. It's hard to convince amateurs that this stuff matters.

I posted what is probably the best ZCD circuit here so far. Certainly the most practical. And mine was right the first time. Hanging a bunch of powered, maybe clocked, poorly designed digital logic on the AC line seems silly to me when a resistor and an optoisolator would work better.

How about totem-pole opto-isolators?

Others have told you where to put the flop, as has John. Have you never heard of a "synchronizer" before?

Because this isn't .basics? Some level of competency is assumed?

You really aren't much of an engineer.

Are you seriously telling us that you don't understand how to connect another D-flop here? That you need a picture and a Spice simulation?

That's incredible.

OK, here you go:

comparator_out-------D Q------ rest of circuit

clock----------------C

Now, go back to sci.electronics.basics for a few years.

He may not have a few years left? For that matter, if you believe in the 2012 dooms year theories, maybe all of us are in a pickle?

Jamie

now where's the fun in that? it wouldn't involve a bunch of discretes, logic and supply

and if it doesn't have lots of parts it looks too simple and it won't convince anyone of the designers "awesomeness"

-Lasse

Two comments: that appnote doesn't address the dangers of slow input edges, and doesn't have numbers for CD4000 flops, which may well be worse than the horrible LS parts.

Also, fig 4 doesn't show a common metastability mode, namely output oscillation. Bipolar master-slave flops are more prone to do that, cmos transmission gate types less likely.

Comparing somewhere up the side of a sine wave, where the slope is lower than at the zero crossing, somehow makes glitches go away?

Please explain how.

Seems to me that each of your output blips depends on *three* edge compares to compute its timing. And timing is line-voltage dependant, which a zero crossing is not.

Slow edges from the comparator have threshold skew hazards. And there's the metastability issue, made worse by the slow edges.

Plus, you've got to float a lot of CD4000-type (high output impedance) logic on the AC line, an invitation for noise spikes to make trouble.

He's a *linear* IC designer. He admits he doesn't "do digital." It shows.