Mains voltage zero crossing detector with optical isolated output

time in a hundred, or one time in a billion.

time in a hundred, or one time in a billion.

Run the sim and zoom in on any of the PE pulses. Next, fiddle with the initial delay of the clock generator. You can tune the delay to narrow down the PE pulse to a runt, much narrower than the counters are spec'd to work with.

The alignment between the comparator output and the clock is random, so sooner or later it will see a clock edge in the danger zone. I'd expect it to screw up roughly a couple of times per hour.

Try it.

In real life, with the slow comparator edge, things will be even worse. That hazard is hard to see in Spice, since all the CMOS parts probably have identical modeled thresholds.

The same hazard exists on every PE pulse.

It has bugs. They are easily fixed, but not if you refuse to look at them. A lot of things fail because people refuse to look at the hazards. That is something you have to fight all the time. It helps to have design reviews with semi-competitive people to catch the stuff that you shy away from seeing.

This bug is a classic beginners' mistake, namely bringing an async signal into a synchronous state machine in multiple places. Serious logic designers spot this hazard instantly.

Did you just learn that word? Better look it up again.

Your data is asynchronous with the clock; bingo metastability. Any second-year EE should see that.

Prevail? Convince you? That's not going to happen. You don't care to learn.

Try your second year of EE again. The problem is obvious.

time in a hundred, or one time in a billion.

Dickless.

That's a different discussion. It's cute, but not necessarily useful. There's probably an analog way to do the same function, probably also not useful. In fact, one of my customers did almost exactly that to find the center of a pulse, an optical reflection off a particle.

Wrong is wrong. No personality is involved in that. We did tell you, about a dozen times, that your circuit has some fundamental logic hazards, and you turned that into some sort of personal challenge.

I still kinda like my 2 or 3 part totem-pole ZCD.

Useless as it may be. ...Jim Thompson

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Stupid old fool. My circuit is cheap, elegant, and works. You took a shot at it, posted an incomplete hairball, and gave up.

Platitude/obfuscation #7 ...Jim Thompson

Is that all you can say any more? Endless repetition is a sure sign of senility.

You did post a hairball, and you did give up. Hey, that deserves repeating. Call that #8.

Stupid old hen. #9.

Poor demented SOB. I'm really getting under your skin, and enjoying it immensely ;-) ...Jim Thompson

You enjoy being a buffoon and a failure? Go for it.

Are you going to ruin my career, like you bragged you did to someone else, even though it took you 18 years to "get even"? OK, I give you until 2030 to ruin mine.

"15" years. You need to improve your reading comprehension. ...Jim Thompson

You're slowing down, so let's go with the 2030 deadline.

Even more simple than my LM339 version, yet with a strong pulse into the opto-couplers at the ZC...

how is it useless? it produces an isolated square wave in sync with the mains. You might complain it is sensitive to noise around the zero crossing, but in that regard your schematic with a flipflop is exactly the same.

you just use more parts and they are not needed since the OP said it was going to a pin on an MCU

-Lasse

Good grief. Power hog. Component-rich. Misses the zero cross by a couple of volts. The HC04 will probably oscillate in its linear region. Why didn't you at least use an HC14?

A minor tweak would at least nominally nail the zero crossing.

--- OK, you've got the sim, so why not modify the schematic and post your solution instead of just alluding to vagaries?

After all, if this is a design review, opinions take a back seat to facts, yes?

-- JF

Less than 1°. Why is your 1° better than my 1°?

There's actually a better way.

Show us. ...Jim Thompson