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Mains voltage zero crossing detector with optical isolated output

The problem with an async hairball like this is precisely that it's so hard to prove safe. For example, this comparator has slow, ballpark 5 us, rise and fall times, and it drives three different chips, so you can't be sure when stuff happens. U12 will go metastable now and then. The width of the PE inputs to the counters isn't clearly defined, so the counter loads could be unreliable. There are just too many potential hazards. Things like this might fail one time in a hundred, or one time in a billion.

This could mostly be fixed by synchronizing the comparator output to the clock in one place, and using only the synchronized signal for subsequent processing.

--

John Larkin, President       Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   

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Reply to
John Larkin
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So, do you like JF's circuit?

--

John Larkin, President       Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME  analog, thermocouple, LVDT, synchro, tachometer
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Reply to
John Larkin

Platitude #1. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
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I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Platitudes #2, 3, 4, 5, 6. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Didn't know "platitude" == "right answer"

Reply to
krw

[...]

There's a typo in JF's message ID. John hit the "P" at the same time as the colon.

news: snipped-for-privacy@4ax.com

Reply to
JW 

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Sure.

http://img15.imageshack.us/img15/3167/zcdl.jpg
Reply to
John Fields 

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Slick!
Reply to
John Fields 

--
Hairball? 

Ha! Exactly as I thought, an invitation for a discussion, from you, is
nothing more than a means of trying to instigate a flame war.
Reply to
John Fields

Since what goes on on the detector side of the opto is inherently galvanically isolated from my circuit by a beam of light, my only concern was with generating a pulse which could drive the emitter side of the opto during/at mains zero crossings.

--
JF
Reply to
John Fields

Hi John,

I think the issue is the supply for the opamp and logic isn't it?

I admit I don't follow quite what it does. But these days once you get above a couple of logic chips I find it can end up easier to do things in a micro.

John Larkins circuit seems well suited as a front-end for that.

--

John Devereux
Reply to
John Devereux

I used to design logic that way, asynchronous edges getting anded and ored all over the place. One day an ex-TI guy straightened me out about synchronous logic design... in 1968, roughly. At TI, they weren't allowed to use the presets or clears of flipflops, even at powerup.

But you expect me to be polite to you, when approximately 100% of your replies to my posts are whiney personal nonsense?

Of course it matters; you don't want to see the logic hazards. Even more important, you would have to really work at it to prove there are no hazards. Logic design like this doesn't scale. And it's not necessary.

And they may improperly load the counters. The PEs are a mess.

time in a hundred, or one time in a billion.

What's the width of the PE pulse from Q3? And what's the required width to reliably load the counter?

--

John Larkin, President       Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME  analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
Reply to
John Larkin

time in a hundred, or one time in a billion.

try delaying V3 by 11.58us, look at the pulse width on PE for U4 and U5 around 1.4ms

for even more fun try 11.575us

-Lasse

Reply to
langwadt

time in a hundred, or one time in a billion.

Did you mean 14.58? That makes a nasty runt on PE.

The 4516 needs 220 ns min PE width. A runt will probably do erratic presets to the various flops. A narrow runt might get missed entirely.

What's also bad is the slow risetime from the comparator, and it drives three separate chips. It's impossible to say what will happen with real-life CMOS parts with different thresholds.

Async logic is just too dangerous to use unless you absolutely have to.

--

John Larkin, President
Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro   acquisition and simulation
Reply to
John Larkin

time in a hundred, or one time in a billion.

maybe there's a difference in version, I ran it on a rather old ltspice

at 11.58u I get a pulse less than 100ns wide, at 11.575us it's not even there

yes at the very least there should be synchronizing flop ahead of it all

indeed.

-Lasse

Reply to
langwadt 

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That's just silly.
Reply to
John Fields

one time in a hundred, or one time in a billion.

Yup, I see the same thing, an arbitrarily narrow runt, at 14.xxx for some reason. But it's an obvious hazard. I've seen this done a lot, probably did it myself once or twice.

One more flop would fix it. Then the actual functionality could be considered.

--

John Larkin, President
Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro   acquisition and simulation
Reply to
John Larkin

No, it's not. Asynchronous resets can cause all sorts of grief coming out of reset. Designing in race conditions isn't a good idea.

You're the one who doesn't understand how the circuit *DOESN'T* work. It's typical stuff of hackers.

No proof necessary. The hazard is built in.

time in a hundred, or one time in a billion.

Clueless.

Reply to
krw

time in a hundred, or one time in a billion.

I can spot a runt-pulse race condition when I see one.

Lasse already spotted one of the specific hazards. Runt pulse on a PE, as expected.

Funny you should describe checking the integrity of your own design as "work against myself in your behalf." Hilarious, actually.

--

John Larkin, President
Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro   acquisition and simulation
Reply to
John Larkin

time in a hundred, or one time in a billion.

--
The delay doesn't matter, since the first half-cycle is just the
circuit learning to walk.

Plot the junction of R4 and R5, the outputs of U8, U3, and U1, and run
the sim out to 50ms and you'll see what'll put a grin on your chops.
:-)

If you've a mind to, run the sim again with V1 set to 340V, 50Hz, and
see what happens.

It's a treat!
Reply to
John Fields

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