Main memory <-> Cpu communication ?

For PPro and Pentium II, the front side bus uses (4) 8-byte wide data transactions as part of a 7-cycle transaction composed of: (1) the transaction cycle, (2) the error cycle, (3) the cache hit cycle, (4) data line 1, (5) data line 2, (6) data line 3, and (7) data line 4. The current transaction, the prior error cycle, the cache hit before that, and an even earlier data line can all operate in parallel.

Each of the chips attached to the front side bus maintain a queue of up to 8 pending transactions, yet to be satisfied. There are inbound and outbound queues in the chipset, read-around-writes, etc. It helps in making effective use of the resources.

Jon

Hi,

I think pentium's and athlon cpu's work as follows with main memory:

CPU Main Memory or CPU Main Memory

See bits are retrieved from main memory in parallel.

However... suppose two 32 bit integers have to be read, added together, and written back.

Does this mean that it works like this ?:

CPU