LV/5V level shifting using 74HC gates

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that simplified enough for you?

ultimate load of LSTTL. There's no way a HC anything looks like LSTTL loading.

Thanks! ...Jim Thompson

oh really? I find that method very usaful, I used it a lot to bring out IO pins for higher voltages at high speed, normally up around 12volts.

Jamie

I some times use a pnp as a cheap constant current source as the pull up instead of an (R). This greatly improves the raise time problem and reduces timing issues if this was to be a critical timing application.

Also I find that some family of logic requires a nice snappy raise and fall for proper operation.

The only hitch I have against using PNP's is their famous failures in the base-emitter junction. They may have corrected this by now but I keep this little note in the back of my head at all times when I have my pencil scribbling away.

Jamie

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=A0 |

=A0 =A0 =A0 | =A0 =A0 =A05 V logic

=A0 =A0 =A0 | =A0 =A0 =A0 |\

----o-----o-| >O-

=A0 =A0 =A0|/

sure for higher voltages, but for 3.3 to 5 HCT is simple an you schematic will use more in base current alone

sure but limited by how much you want to spend on pull up current HCT is ~20ns

-Lasse

snipped-for-privacy@fonz.dk a écrit :

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I use that a lot :

On rising edge the cap gets you through the threshold AFAP and the pull finishes the swing (when it has time)... On falling edge all is reseted.

Yep. Gives rail-to-rail drive to 74HCxx. As I previously posted in...

Date: Mon, 27 Aug 2012 09:52:23 -0700 Message-ID:

Originally posted here by me on 9/18/2006 :-) ...Jim Thompson

OOOH! Sneaky! And right about when I was wondering if I could breadboard it up with a 4007, I paged down to the second panel...

The only weakness, is that it requires two power supplies (but that's part of the problem statement). It's easy to generalize to (for instance) +5 logic to +/-5V.