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Hardware interfacing to LV FPGAs

Hi, After many years in the 5 volt world, I'm making my first tentative steps into FPGAs, which tend to deal with lower voltages. It seems that below 5 volts, things aren't as clear, there are references to 3.3volts, 2.5 volts and even lower. Unlike 5V families, which are clearly specified to run at that voltage, the lower voltage stuff seems to be specified with a much wider supply range.

Is there a web reference that someone oculde suggest that clarifies the situation, my browsing so far hasn't come up with anything particularly clear. Ideally, there'd be a standard that covers glue logic such as gates and buffers, and interface devices such as ADCs, that interfaces cleanly to FPGAs specified for 3.3V connectivity. A level translator that goes between

3.3 and 5 would also be nice.

Any assistance appreciated.

Reply to
Bruce Varley
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It is something I am going to be taking a closer look at myself as well. I have noted that there are some level translation chips between the 1.8V and

5V worlds (1.8V seems to be an optimum for a multi-core processor I am looking at). However, I might end up designing my own level translation and isolated interfaces between the multi-core processor and the Real World. 
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Reply to
Paul E. Bennett

We've used these for this very application on Xilinx FPGA:

SN74AVC8T245PW family TXS0108EPWR

The most tricky bit we found was interfacing to 5V.

The TXS.. is a bit on the slow side but it is autosensing bidirectional and we've got this between a 3.3V micro and 5V LCD, and on a 2.5V to

3.3V "slow" interface.

We've used the other family for the lower 2.5V 3.3V stuff. These are also bidirectional but you have to select direction and you can't control pins individually.

The voltages lower than 2.5V tend to be for the core of the FPGA rather than the IO so may not need the interfacing.

HTH a bit

Dave.

Reply to
DaveN

It is pretty common these days for 5V parts to have 3.3V compatible inputs -- look at the "VIL" and "VIH" specs in the data sheet. If that's not the case, 74HCTxx and 74ACTxx logic is nominally designed to be 5V CMOS that's compatible with TTL, but that also makes it compatible with

3.3V CMOS logic.

I have been in the position of sadly rejecting an otherwise nice 5V peripheral in favor of the 2nd-place part because 1st-place would have needed interface chips to work with a 3.3V FPGA, and 2nd-place had 3.3V compatible inputs.

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Reply to
Tim Wescott

Thanks guys, the responses have been helpful. One thing that did occur to me after I sent the post is that for driving LV inputs one possibility would be open collector LSTTL (or equiv) with pullups to 3.3V. Is that going to be viable, or am I missing something?

Reply to
Bruce Varley

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You could also just use a schottky diode - anode to FPGA and pullup to

3v3 on FPGA.

You could also use a resistive divider with the /right/ value cap across the uppper resistor. :)

Reply to
Rocky

You'll have to watch the speed. The rising edge from the pull-up could be too slow (or the current too high for low resistor values)

Reply to
Arlet Ottens

Have you checked your candidate part to see if the inputs are 5V tolerant? This used to be the case with older Xilinx parts, but I just did a quick check and it looks like the absolute brand-newest stuff from Xilinx isn't. OTOH, a look at this page:

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It coughs up slews of 5V tolerant low-voltage logic, including 8x buffers.

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Reply to
Tim Wescott

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