Hi,
I'm trying to supply a clock to one of the 3.3V GCLK inputs on a Xilinx Virtex-II FPGA. Due to other requirements I need to use a 5V VCO (TI TLC2932) to drive this input, but I'm having some problems.
I thought about using a voltage divider to convert the 5V VCO output to
3.3V, but the PCB trace between the VCO and the FPGA is reasonably long, so I need to include some termination. This is where I run into difficulty.
I was going to terminate the line with a 33Ohm series resistor near the VCO. This would be fine if the VCO had a low output resistance, as I could just use something like a (33 - VCO_output_resistance)Ohm resistor in series and a 75 Ohm to ground, which should give me 3V with 30Ohm looking back into the source from the transmission line.
However, the VCO provides a 5V square wave at 2mA, so would I be right in saying that it's got a 2.5k source impedance?
If that is correct then this is where I get stuck. I can divide the signal down to 3V with a 5k pull down at the output, but the equivalent resistance of this will be 1.7k. Alternatively, I could use a 33Ohm pulldown on the output which would give me my 33 Ohm terminating resistance, but the signal would only be 65mV.
Does anyone have any hints on how I can source terminate this VCO to
33Ohms whilst level translating from 5V to 3.3V?
Steve