Actually, it is probably more complicated than that, and simpler. I know that the the time step processes gave them fits, especially for fast transitions, but that when they were done they were pretty happy about it. But, basically, they did actually digital logic, and then wrapped an AtoD and DtoA around it. When they did PLSyn for programmable logic, like Xilinx FPGAs, they used the logic expressions provided for the PLA and the timing expressions, and then did the A-D translations at the borders. The PSpiceHDL tool would have used NC-SIM as the VHDL or Verilog simulator, with the same types of translations, including IBIS models. However, that would have sold in the $20K range, and been a valid replacement for $200K tools, so they just eliminated the entire development team...
Charlie