I picked up the macromodel from AD(TI) for this IC. I=20 am using the manual to try to figure out how to=20 incorporate the model in a circuit idea, but i hit up=20 against errors. This one has me baffled though. =20
The error i am getting is:
"Port(pin) count mismatch between the definition of 'ad734.cir' and = instance xu1. The instance has more connections than the definition."
I don't understand why i am getting this error. I would like to better understand how to make this work.
Here is example test circuit:
+++++ Version 4 SHEET 1 2476 680 WIRE 800 -1120 688 -1120 WIRE 688 -1088 688 -1120 WIRE 800 -1088 800 -1120 WIRE 208 -1008 112 -1008 WIRE 0 -992 0 -1040 WIRE 208 -992 208 -1008 WIRE 640 -896 448 -896 WIRE 800 -896 800 -1008 WIRE 800 -896 640 -896 WIRE 208 -864 208 -912 WIRE 320 -864 320 -1040 WIRE 320 -864 208 -864 WIRE 0 -848 0 -912 WIRE 112 -848 112 -1008 WIRE 112 -848 0 -848 WIRE 0 -816 0 -848 WIRE 448 -608 448 -896 WIRE 496 -608 448 -608 WIRE 704 -608 704 -656 WIRE 704 -608 640 -608 WIRE 496 -576 464 -576 WIRE 656 -576 640 -576 WIRE 464 -544 464 -576 WIRE 464 -544 432 -544 WIRE 496 -544 464 -544 WIRE 672 -544 640 -544 WIRE 672 -528 672 -544 WIRE 816 -528 672 -528 WIRE 432 -512 432 -544 WIRE 464 -512 464 -544 WIRE 496 -512 464 -512 WIRE 672 -512 672 -528 WIRE 672 -512 640 -512 WIRE 464 -480 464 -512 WIRE 496 -480 464 -480 WIRE 768 -480 768 -608 WIRE 768 -480 640 -480 WIRE 192 -448 192 -480 WIRE 192 -448 48 -448 WIRE 496 -448 192 -448 WIRE 656 -448 640 -448 WIRE 464 -416 464 -480 WIRE 496 -416 464 -416 WIRE 672 -416 640 -416 WIRE 672 -304 672 -416 WIRE 704 -304 704 -320 WIRE 704 -304 672 -304 WIRE 768 -304 768 -480 WIRE 768 -256 768 -304 WIRE 48 208 48 -448 WIRE 48 368 48 288 =46LAG 48 368 0 =46LAG 688 -1088 0 =46LAG 0 -1040 VP =46LAG 320 -1040 VN =46LAG 0 -816 0 =46LAG 704 -656 VP =46LAG 704 -320 VN =46LAG 768 -256 0 =46LAG 432 -512 0 =46LAG 192 -480 Ain =46LAG 640 -896 C0 SYMBOL voltage 48 192 R0 WINDOW 3 46 82 Left 0 WINDOW 123 46 50 Left 0 WINDOW 39 47 110 Left 0 SYMATTR Value SINE(0 1 220 0 0 0) SYMATTR Value2 AC 1 0 SYMATTR SpiceLine Rser=3D1 Cpar=3D100p SYMATTR InstName V1 SYMBOL voltage 800 -1104 R0 WINDOW 3 43 69 Left 0 WINDOW 123 43 41 Left 0 WINDOW 39 44 95 Left 0 SYMATTR Value SINE(0 1 10.7M 0 0 0) SYMATTR Value2 AC 1 0 SYMATTR SpiceLine Rser=3D5 Cpar=3D1p SYMATTR InstName V5 SYMBOL voltage 0 -1008 R0 SYMATTR InstName V7 SYMBOL voltage 208 -1008 R0 SYMATTR InstName V8 SYMBOL AD734 576 -560 R0 SYMATTR InstName U1 SYMATTR Prefix X1 X2 U0 U1 U2 Y1 Y2 VN ER Z2 Z1 W DD VP SYMATTR SpiceModel ad734.cir SYMBOL cap 704 -592 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C2 SYMATTR Value 100n SYMBOL cap 704 -288 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C3 SYMATTR Value 100n TEXT 48 -1088 Left 0 !.subckt ad734.cir TEXT -32 392 Left 0 !.tran 10m=3D=3D=3D=3D=3D
Here is the downloaded macromodel:
+++++- AD734 SPICE Macro-model 4/92, Rev. B
- AAG / PMI
- Revision History:
- Removed input signal current compensation: GX1,GY1,GZ1
- Added Isy vs. Vsy
- Copyright 1992 by Analog Devices, Inc.
- Refer to "README.DOC" file for License Statement. Use of this model
- indicates your acceptance with the terms and provisions in the License = Statement.
- Node assignments
- X1
- | X2
- | | UO
- | | | U1
- | | | | U2
- | | | | | Y1
- | | | | | | Y2
- | | | | | | | VN
- | | | | | | | | ER
- | | | | | | | | | Z2
- | | | | | | | | | | Z1
- | | | | | | | | | | | W
- | | | | | | | | | | | | DD
- | | | | | | | | | | | | | VP
- | | | | | | | | | | | | | | .SUBCKT AD734 10 11 49 50 51 20 21 200 58 31 30 77 54 100
- EREF 300 0 POLY(2) 100 0 200 0 (0,0.5,0.5)
- X INPUT STAGE & POLE AT 40 MHz
- CINX 10 11 2E-12 IBX1 10 0 DC 50E-9 IBX2 11 0 DC 50E-9 EOSX 12 10 POLY(1) 18 300 15E-3 1 RX1 12 13 25E3 RX2 13 11 25E3
- GX1 300 14 12 11 1E-6 RX3 14 300 9.995E5 CX1 14 300 3.9809E-15 VX1 100 15 DC 3.1875 DX1 14 15 DX VX2 16 200 DC 3.1875 DX2 16 14 DX
- X INPUT STAGE COMMON-MODE REJECTION AND ZERO 40 kHz
- ECMX 17 300 13 300 56.234 RCMX1 17 18 1E6 CCMX 17 18 3.9789E-12 RCMX2 18 300 1
- Y INPUT STAGE & POLE AT 40 MHz
- CINY 20 21 2E-12 IBY1 20 0 DC 50E-9 IBY2 21 0 DC 50E-9 EOSY 22 20 POLY(1) 28 300 10E-3 1 RY1 22 23 25E3 RY2 23 21 25E3
- GY1 300 24 22 21 1E-6 RY3 24 300 9.995E5 CY1 24 300 3.9809E-15 VY1 100 25 DC 3.1875 DY1 24 25 DX VY2 26 200 DC 3.1875 DY2 26 24 DX
- Y INPUT STAGE COMMON-MODE REJECTION AND ZERO 80 kHz
- ECMY 27 300 23 300 56.234 RCMY1 27 28 1E6 CCMY 27 28 1.9895E-12 RCMY2 28 300 1
- Z INPUT STAGE & POLE AT 40 MHz
- CINZ 30 31 2E-12 IBZ1 30 0 DC 50E-9 IBZ2 31 0 DC 50E-9 EOSZ 32 30 POLY(1) 38 300 20E-3 1 RZ1 32 33 25E3 RZ2 33 31 25E3
- GZ1 300 34 32 31 1E-6 RZ3 34 300 1E6 CZ1 34 300 3.9789E-15 VZ1 100 35 DC 3.1875 DZ1 34 35 DX VZ2 36 200 DC 3.1875 DZ2 36 34 DX
- Z INPUT STAGE COMMON-MODE REJECTION AND ZERO 40 kHz
- ECMZ 37 300 33 300 56.234 RCMZ1 37 38 1E6 CCMZ 37 38 3.9789E-12 RCMZ2 38 300 1
- DENOMINATOR CONTROL & INTERNAL REFERENCE
- QU1 100 49 50 QNU RU1 50 51 28E3
- VU 100 52 QU2 52 0 53 QNU RU2 53 54 0.001 IU 53 200 DC 10E-6 =46U1 300 55 VU 1.01 RU3 55 300 1E6
- VR1 57 200 DC 8 QR 59 57 58 QPU RR 57 58 1E5 VR2 59 200 =46U4 300 56 VR2 1 RU4 56 300 28E3
- EU 60 300 POLY(3) 50 51 55 300 56 300 (0,1.0101,1,1.0101) RU5 60 300 1E6
- 250 MHz MULTIPLIER CORE
- EXY 46 300 POLY(2) 14 300 24 300 (0,0,0,0,1) RXY 46 300 1E6 GXY 300 47 46 300 1 GU 47 300 POLY(2) 60 300 47 300 (0,0,0,0,1) RU 47 300 1E12 CU 47 300 6.65E-9 EW 48 300 POLY(2) 47 300 34 300 (0,1,-1) RW 48 300 1E6
- OUTPUT AMP BUFFER
- GW 64 300 48 300 1 QW1 100 0 61 QNW QW2 200 0 62 QPW QW3 63 62 64 QNW QW4 65 61 64 QPW RW1 100 63 1 RW2 65 200 1 IW1 100 62 DC 100E-6 IW2 61 200 DC 100E-6 VW1 100 66 DC 10 DW1 66 63 DX VW2 67 200 DC 10 DW2 65 67 DX
- OUTPUT AMP GAIN STAGE
- GW1 300 68 100 63 1 GW2 68 300 65 200 1 RW3 68 300 1.38E3 CW1 68 300 19E-9 VW3 100 69 DC 3.8 DW3 68 69 DX VW4 70 200 DC 3.8 DW4 70 68 DX
- TRANSIENT SUPPLY CURRENT COMPENSATION
- DCC1 80 100 DX GCC 0 80 48 300 1 DCC2 0 80 DX DEE1 81 0 DX GEE 81 0 300 48 1 DEE2 200 81 DX
- POLE AT 17.5 MHz
- GW3 300 71 68 300 1E-6 RW4 71 300 1E6 CW2 71 300 9.0946E-15
- IDC 100 200 DC 4.0125E-3 RDC1 100 78 3.2E3 RDC2 78 200 3.2E3 DO1 100 72 DX GO1 72 200 76 71 25E-3 DO2 200 72 DY DO3 100 73 DX GO2 73 200 71 76 25E-3 DO4 200 73 DY VSC1 74 76 DC 0.4 DSC1 71 74 DX VSC2 76 75 DC 0.4 DSC2 75 71 DX GO3 76 100 100 71 25E-3 GO4 200 76 71 200 25E-3 RO1 100 76 40 RO2 76 200 40 LO 76 77 100E-9
- MODELS USED
- .MODEL QNU NPN (BF=3D100 IS=3D1E-16) .MODEL QPU PNP (BF=3D100 IS=3D1E-16) .MODEL QNW NPN (BF=3D1E9 IS=3D1E-15) .MODEL QPW PNP (BF=3D1E9 IS=3D1E-15) .MODEL DX D(IS=3D1E-15) .MODEL DY D(IS=3D1E-15 BV=3D50) .ENDS AD734
=3D=3D=3D=3D=3D
Here is the symbol i created:
+++++ Version 4 SymbolType CELL RECTANGLE Normal 64 187 -80 -85 TEXT -58 -106 Left 0 AD734 SYMATTR ModelFile AD734.cir SYMATTR Prefix U SYMATTR SpiceModel AD734 PIN -80 -48 LEFT 8 PINATTR PinName X1 PINATTR SpiceOrder 1 PIN -80 -16 LEFT 8 PINATTR PinName X2 PINATTR SpiceOrder 2 PIN -80 16 LEFT 8 PINATTR PinName U0 PINATTR SpiceOrder 3 PIN -80 48 LEFT 8 PINATTR PinName U1 PINATTR SpiceOrder 4 PIN -80 80 LEFT 8 PINATTR PinName U2 PINATTR SpiceOrder 5 PIN -80 112 LEFT 8 PINATTR PinName Y1 PINATTR SpiceOrder 6 PIN -80 144 LEFT 8 PINATTR PinName Y2 PINATTR SpiceOrder 7 PIN 64 144 RIGHT 8 PINATTR PinName VN PINATTR SpiceOrder 8 PIN 64 112 RIGHT 8 PINATTR PinName ER PINATTR SpiceOrder 9 PIN 64 80 RIGHT 8 PINATTR PinName Z2 PINATTR SpiceOrder 10 PIN 64 48 RIGHT 8 PINATTR PinName Z1 PINATTR SpiceOrder 11 PIN 64 16 RIGHT 8 PINATTR PinName W PINATTR SpiceOrder 12 PIN 64 -16 RIGHT 8 PINATTR PinName DD PINATTR SpiceOrder 13 PIN 64 -48 RIGHT 8 PINATTR PinName VP PINATTR SpiceOrder 14=3D=3D=3D=3D=3D