LTSpice model for a SiC MOSFET

The 1kV source is good for about 10uA. Do pay attention.

If you'd answered those questions accurately, when originally asked, you would have had my attention.

RL

If you look at the subject line of the thread, you will note that I was after Pspice model for a particular transistor. I did mention that the

If you'd care to quote the questions you asked, and post a couple of my "inaccurate answers" I might take you seriously, but you've asserted that I was acting like a troll on several occasions, so it is unlikely.

A 3.3v zener will probably leak more than 10uA. Low voltage zeners are awful.

And he wants 3 mA out... I think.

Bill was the confused person.

The problem gets much more interesting with 10 uA in and 99% efficiency requirement.

A Baxandall isn't going pull microamps at 1 KV.

It's not any kind of answer to the question I was asked.

The original question talked about 50% efficiency which would have been

John Larkin does like posting claims like that. He gets confused at least as often as the rest of us, but is remarkably reluctant to admit it.

There never was a 99% efficiency requirement. Jim Williams got 93% efficiency going the other way, but that's a very different problem, and he worked on it for years, if his series of applications notes are anything to go by.

The examples I've simulated pulls about 10uA - some of that is being dissipated in the circulating current in the tank circuit in the transformer, but the MOSFets dissipate a certain amount of energy every time they turn on and off. One of the virtues of the Baxandall configuration is that the switching happen when there isn't much of a voltage drop across the transistors when they are switching, so it isn't too bad.