LTSpice: how to simulate a current limiter?

Jul 23, 2018 7 Replies

Hello,



in my sims I often need to simulate a soft-saturable current limiter, usually for AC. The exact construction of such a limiter is not important from the core circuit's perspective. As long as its I(U) is sigmoid or arctan-like, it's fine. What's the simplest way to express such a building block in Spice? Making it out of discretes every time adds considerable obscurity to the sim and is time-consuming.



Best regards, Piotr


How about a current source in parallel with a diode?

John Larkin Highland Technology, Inc lunatic fringe electronics

Am 23.07.2018 um 06:34 schrieb Piotr Wyderski:

.FUNC or Voltage Dependent Current Source using rables or polynomials.

--> Help

Good luck - Udo

Am 23.07.2018 um 11:02 schrieb Newdo:

::tables.

I don't understand the combination of (apparently) magnetic saturation and current limiting, but you can always use a flux based model like this for saturation:

  • Saturable Core Model, copied from:
  • _SPICE Models For Power Electronics_, Meares and Hymowitz.
  • .SUBCKT INDSAT 1 2 PARAMS: VSEC=1e-4 LMAG=1e-5 LSAT=1e-7 FEDDY=1e6 F1 1 2 VM1 1.0 G2 2 3 1 2 1.0 E1 4 2 3 2 1.0 VM1 4 5 0.0 RX 3 2 1E9 CB 3 2 {VSEC/500} IC=0 RB 5 2 {LMAG*500/VSEC} RS 5 6 {LSAT*500/VSEC} VP 7 2 250 VN 2 8 250 D1 6 7 DCLAMP D2 8 6 DCLAMP .MODEL DCLAMP D ( CJO={3*VSEC/(6.28*FEDDY*500*LMAG)} VJ=25 M=0.01 RS={LSAT/VSEC} ) .ENDS

Roughly speaking, LMAG / LSAT = mu_r, VSEC is the flux at saturation, and FEDDY is the dominant pole rolloff.

As-is, it's pretty reasonable for ferrites. Roll-off for laminated materials is better approximated by a k*sqrt(f) impedance in parallel. Powder materials saturate more gradually, so DCLAMP might be replaced with a POLY in that case.

Tim

Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website: https://www.seventransistorlabs.com/ "Piotr Wyderski" wrote in message news:pj3lse$qmc$1@node2.news.atman.pl... > Hello, > > in my sims I often need to simulate a soft-saturable current limiter, > usually for AC. The exact construction of such a limiter is not important > from the core circuit's perspective. As long as its I(U) > is sigmoid or arctan-like, it's fine. What's the simplest way to > express such a building block in Spice? Making it out of discretes > every time adds considerable obscurity to the sim and is time-consuming. > > Best regards, Piotr

Thanks, you solved my other problem. :-)

In this case I don't have any magnetics, just want to simulate two back-to back connected depletion-mode MOSFETs/JFETs that form an AC current limiter without the need to handicraft such a limiter every time. Firstly, because it takes a lot of time to select the components properly. The second reason is the lack of good DMOSFET models in LTSpice. Fortunately the available JFETs work up to the megavolt range, but it is a kludge.

I'd like to have a single box with two parameters, I_SAT and, say, the U for which I is 1-1/e of I_SAT. Or 90%, whatever. Just don't know how to create such a box in Spice.

[snip something very useful]

Best regards, Piotr

Well, you can always do what you'd do for limiting voltage: back to back diodes. Then put a gyrator in front of it, so current and voltage are swapped around. (A gyrator is just a pair of dependent sources, same as you make a DC transformer.)

I can write it out and do some example circuits if you like.

Tim

Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website: https://www.seventransistorlabs.com/

Phil H and later moi posted the lnd150 model, it's somewhere on the web. and good from ~1-2mA and below. Then something like the DN2540 up to ~100mA. That's two models with R knobs. How much current do you need? George H.

Fortunately the available JFETs work

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