LTspice Loafing?

Yes. However, I could have another go and do another model from scratch, could probably speed it up a fair chunk. Overtime, I have his habit of breaking stuff that worked, so its possible its now now strange things. Recently, I noticed that I have inadvertently removed the sweep of resistance in dc sweep setup list box. Now fixed.

Note, a lot of the SS examples, are where I just wanted to create demos that worked, rather than a viable real "design". They are meant to demonstrate all the features, and the sort of problems you can solve in SS. I think they are way more extensive than any other simulators examples. There is a lot of behavioural, system examples.

Most haven't been updated since they were crated. That example actually has an external gate resister to get convergence, but since then I added RG to the mosfet core model itself. My mosfet 1 now supports an "enhanced" LTSpice VDMOS mode.

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Its all relative though. Using my aforementioned expensive $100k per seat, per year, Cadence suite, I often run simulations that last 1/2 or 1 hour. Main top levels can take a day, some several days. PSNoise is the main killer.

I started with a HP85 in around 1982 for AC analyses, moving up to DOS PSpice in 1985 on an XT, so I am sure you can appreciate, that today, 7 secs for a SMPS, is sheer Luxury. I used to dreeeeeem of such a life when I was knee high.

On that HP, I wrote my first complex number Gaussian elimination with partial pivoting routine. I also learned how to move graphic objects on screen by getting the prior background and XORing stuff. However, all this software stuff is pissing about really. After 150k lines of SS C++ code, I am still just a hack. My expertise is really only in analog design.

I wrote it from scratch after Mike was lording it over everyone with his LT

Anyone that wants my full source code to my xspice version is welcome to it. Just email me.

It would be worth copying in my ASK routines for BSIm3 and BSim4 to ngspice. I added the code so that all transient terminal currents (d, g, b,s) are available. The original only has drain. Its an indispensible feature.

I have considered setting up the latest ngspice to work better with SS. Like having it as an alternative, engine.

[..]

I will see if I can dig it out.

TRTOL=1 is a safe option.

For things like Sigma-Dalta, much more risky to increase, especially the tolerance. Its the bit about chaos that does it :-)

My SS 1st order S-D is ok with retol=1m and trtol=5, but the 2nd order S-D has something like trtol=1 and relto=100u. It can really mess-up with looser values.

-- Kevin Aylward

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Perfectly documented! Unfortunately MUCH too small.

LTspice: 8.221 seconds. NGSPICE: 1.450 seconds. SuperSpice: (don't have it on this machine)

| Original .options: | .OPTIONS GMIN=1E-9 ITL4=5000 PIVTOL=1E-9 RELTOL=0.0001 RSHUNT=1E7 METHOD=GEAR MAXORD=2 | .TRAN 1E-9 0.0005 0 1E-7 UIC

LTspice options (alternate solver): .options reltol=1m method=gear nomarch .tran 0 500u 10u uic

NGSPICE options: .options reltol=1m method=gear .tran 0 500u 10u 20n uic

-marcel

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mhx

Note that SS automatically prints out the simulation clock time at the end of each run type.

| .TRAN 1E-9 0.0005 0 1E-7 UIC

Now rerun LTspice with a blank setting for max time step. Then check if the waveform is ok.

You usually need to let LTSpice do what it wants to do for any comparison to be valid. It uses different algos

-- Kevin Aylward

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Kevin Aylward
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The above .tran line already has TMAX blank. The "10u" is TSTART, the time when to start saving data (I skip the transient at the start). Or did you mean something else?

I think I did.

BTW, do you, by chance, know what LTspice tries to tell us with messages like these?

|| Changing Tseed to 1e-016 || Heightened Def Con from 3e-010 ++++++++++++to 3.3e-009

-marcel

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mhx

Looks like Mikes randomly deciding whether or not to nuke Iran.

-- Kevin Aylward

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