LTspice

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

LTSpice gives inductors a default parallel resistance. This can be overridden by specifying a value (e..g 1e24) in the inductor properties. I've had to do this for the motional inductance of high-Q crystals.

"Andrew Holme" schrieb im Newsbeitrag news:PFYBo.44369$ snipped-for-privacy@newsfe19.ams...

Hello Jim,

I fully agree with Andrew.

Right-mouse-click on the inductor. Enter a high value in Rpar, e.g. the mentioned 1e24. I guess Rpar=0 will also treated as deleting the default value.

Best regards, Helmut

Doesn't fix it. Tried both Trap and Gear as well. ...Jim Thompson

Looks like LTspice will converge for Q

Doesn't this only happen with "drawn" inductors? I'm working from a netlist generated elsewhere.

I finally got it to run by reducing the crystal "Q" down to 5K. ...Jim Thompson

"Jim Thompson" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

Hello Jim,

If it doesn't run in LTspice but in PSPICE, you may have done something wrong. Please send me your circuit. I will show you how to get it simulated with LTspice.

Best regards, Helmut

It's not drawn in LTspice. I simply opened a (PSpice) .CIR (and included .NET) file and ran in LTspice. Problematic: It's designed under XFAB CX06, so NDA'd. If you have CX06 libraries yourself, I can send it, otherwise you can't run it... I can't share that info. ...Jim Thompson

Sent without libraries, in case you can spot a set-up error. Thanks! ...Jim Thompson

On Mon, 08 Nov 2010 18:25:24 -0700, Jim Thompson wrote:

How are you modeling the crystal? I generally do it as a capacitor with series inductance and resistance, and parallel capacitance.

Like:

Version 4 SHEET 1 880 680 WIRE 80 128 32 128 WIRE 192 128 160 128 WIRE 32 144 32 128 WIRE 192 144 192 128 WIRE 400 144 256 144 WIRE 192 224 192 144 WIRE 256 224 256 144 WIRE 32 288 32 224 WIRE 224 288 32 288 WIRE 400 288 400 224 WIRE 400 288 224 288 FLAG 224 288 0 SYMBOL MISC\\XTAL 192 160 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName Y1 SYMATTR Value {C1} SYMATTR SpiceLine Rser={ESR} Lser={Ls} Cpar={C0} SYMBOL cap 256 208 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName CL1 SYMATTR Value {cl} SYMATTR SpiceLine Rser=0 SYMBOL voltage 32 128 R0 WINDOW 123 24 116 Left 0 WINDOW 39 24 128 Left 0 SYMATTR InstName V1 SYMATTR Value "" SYMATTR Value2 AC 5.5m SYMATTR SpiceLine Rser=0 Cpar=0 SYMBOL res 384 128 R0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res 176 144 M270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R2 SYMATTR Value 50 TEXT -240 -96 Left 0 !*serial resonant frequency:\n.param fs=32.768e3\n \n*difference between serial and parallel resonance:\n;.param df=1k\n.param df=fs*c1/(2*C0)\n \n*Effective Series Resistance: \n.param ESR=70k\n \n*Holder Capacitance:\n.param C0=1.3p\n \n*Motional Capacitance:\n;.param C1=2.0*c0*df/fs\n.param C1=2.0f\n \n*Motional Inductance:\n.param Ls=1/(4*pi*pi*fs*fs*C1) TEXT 232 232 Left 0 ;Load Capacitance TEXT -240 176 Left 0 !;.step param Cl 1p 12.5p 1p TEXT -240 192 Left 0 !.ac lin 1000 32.75k 32.8k TEXT -240 136 Left 0 ;Typical Epson Toyocom 32768kHz FC255\nMax Drive 0.5 microwatt TEXT -240 160 Left 0 !.param Cl=7p

\n*difference between serial and parallel resonance:\n;.param df=1k\n.param df=fs*c1/(2*C0)\n \n*Effective Series Resistance: \n.param ESR=70k\n \n*Holder Capacitance:\n.param C0=1.3p\n \n*Motional Capacitance:\n;.param C1=2.0*c0*df/fs\n.param C1=2.0f\n \n*Motional Inductance:\n.param Ls=1/(4*pi*pi*fs*fs*C1)

microwatt

Your schematic has text on top of the circuit :-(

I model XTAL as series L-R-C paralleled with a C

To make it work in LTspice I had to add, per Helmut's instruction, the Rpar gimmick. ...Jim Thompson

Should just be the "Load Capacitance" label, put there for "clarity"

Well, that's what I did, really.

You can get rid of the default inductor damping in Control Panel/Hacks/ "Supply minimum inductor damping if no rpar is given." (uncheck) and "Always default inductors to rser=0" (check)

I don't much like the default behavior,either.

Remember the "DC Current in Parallel Inductors" thread in s.e.d? That needed the default series resistance getting rid of to make the simulation agree with the theoretical differential equations.

Got it all working. The slippery slope appears to be that "un-drawn" (from an existing netlist or subcircuit) inductors don't get netlisted with Rpar.

Fabulous speeds... like TWICE as fast as PSpice!

If I can figure out how to use PSpice Probe as a post processor I'll be a convert ;-) ...Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Well, it's not like Cadence has bothered to update the PSpice engine in years now...

Do you have a multi-core CPU? I seem to recall that these days LTspice knows to take advantage of that, whereas I can't imagine that PSpice does.

Isn't Probe freely available these days since it was once bundled with the free cut-down ("educational") versions of PSpice? That'd be pretty cool -- I expect a lot of people would like to use it then.

PSpice doesn't. Does dual-core speed-up LTspice?

I'm about to try a CSDF output, which, in theory, Probe can read... but that may be like wonderfully useless EDIF :-( ...Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

For almost two years now purportedly it does... old post from Mike Engelhardt,

"A major update for LTspice was released today. LTspice IV, formerly known as LTspice/SwitcherCAD III, features multi-threaded solvers to better utilize current multi-core processors. Also included are new SPARSE matrix solvers that deploy self-authoring code which is assembled and linked on the fly in order to approach the theoretical flop limit of current FPU's. Large circuits run ~3 times faster on quad core processors. Small circuits will run at about the same speed as the prior version of LTspice.

Developing a parallel processing version of SPICE has been a long standing challenge in circuit simulation that has been met with limited commercial success. LTspice IV reflects a review of the techniques that have been attempted and implements proprietary methods that allow it to efficiently parallelize tasks that require as little as 5µs to run single-threaded in proportionally less time with additional processing cores."

Let us know how it goes...

---Joel

The format _isn't_ CSDF :-(

It's columnar suitable only for use in Excel, or to roll your own excitations.

So... use LTspice for quick solutions, PSpice as a design review "Publisher" :-) ...Jim Thompson

Whined before thinking. Those columnized data points can be quickly re-run thru PSpice, then Probed :-)

Maybe I can get Aaron to write an automation tool converting from LTspice text to CSDF ;-) ...Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Is CSDF format documented anywhere? Or is it relatively obvious what the structure is from looking at a file?

It's a messy set of ; separated headers, then TAB (I think) separated data points.

The LTspice text output looks perfect for Excel processing. Maybe I can see a way to process and add headers, using UltraEdit. ...Jim Thompson