LT Spice question

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OK maybe just invert it then? Or is there a power supply issue.

but at G=3D+1 they can be like a Lamborghini

Yes or throw away some signal and add some gain. (as JT suggested) A little resistance here and there can be a good thing.

George H.

I can do all that stuff and more. Trouble is, I have a regular job in Livermore. Until the government goes broke of course, which will probably come in 1-3 years. If we get shut down I'll stop by your shop in SF and show you my CV. Or perhaps if they ask me to inspect 2000 pieces of equipment again.

That's an interesting author. Oh joy, another "Verilog by Example" book. Maybe I'll buy it on Monday. Have you seen it already and can offer a "mini-review?" I have these two already:

I forget which one tells the reader to divide down the clock using a counter, then to clock other experiments with the logic derived clocks.

Needless to say, this is not a popular technique in the real world. I tend to have to get my work done before I have time to finish reading my books, so I haven't had a chance to study them in depth. One wonders why I have them at all? Well, I still have a lot to learn in order to tackle some upcoming projects, so a few weeks of serious book study is in the cards once I get my F2812 and Spartan 3E PCBs done.

Larkin has been trying (since April) to make a boot-strapped ramp, so he needs +1

...Jim Thompson

The brute force would be to use two unity gain inverting amps. If the non-linearity is the big concern maybe you could try a "gooser", 100ohms in series with 2.2pF from IN- to GND. You'd have to check phase margins. But that 100MHz ringing you have there is suspicious, that could hardly come out of the amp.

That is a cool color. I have never seen such a deep blue offered for FR4 material.

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=A0 =A0 ...Jim Thompson

=A0 =A0| =A0 =A0mens =A0 =A0 |

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=A0 =A0 =A0 |

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Hmm OK, I've barely done any bootstrapping. But can't you put the same amount of gain in the bootstrap circiut too?

George H.

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Last April I suggested a way to insert a current to produce the level shift, but I was clucked :-( ...Jim Thompson

Here's the circuit:

ftp://jjlarkin.lmi.net/Ramp.JPG

Inversion won't work - I need a high impedance load on the ramp capacitor - and a gain of 1 makes the bootstrap current source simple and accurate.

It works, but I'm getting linearity errors equivalent to about 180 ps out of a 16 ns ramp, around 1%. That's not bad for a 16 nanosecond ramp, but the customer (unreasonably) wants better. Don't know why, there's only a few billion dollars per year affected by this error.

I've done 0.1% for a 40 ns ramp before, using a real current source, so this shouldn't be all that difficult. The AD8014, while cheap and low power, wasn't the best choice, and it sure looks like the Spice model isn't very accurate.

The ramp at the capacitor, seen with a fet probe, looks perfect.

Sigh, I suppose I'll have to get in there and start soldering. I am waiting for some software to get done that gives me better analytics on the linearity.

John

Our boards are yellow silk on blue solder mask. That photo was taken by skylight, north side of the building, so it looks very blue.

This board is a hodge-podge of functions, and the fast ramps are just a small piece of the process. We're just now getting the FPGA coded, the ARM coded, and we're developing PC programs to talk to it and manage it and do analytics. The box this goes in has 68 connectors, 19 of them fiber optics. Beast.

John

IF a DC shift is ok or can be compensated for, how about using a fast follower? Possibly a little FET. That guarantees a high impedance.

is it just the way the picture is taken that makes it look like there's no flooding on the top copper layer? or is there a reason for it

-Lasse

It still has to drive the bootstrap, which would load a fet and cause new linearity errors. So I'd have to go to an active current source. Too much like work.

The ramp at the cap looks great, so the opamp loading isn't a problem. It's making the opamp follow accurately that's the issue.

John

No layer 1 flooding. It's an 8-layer board, with a power plane on 2, ground on 4.

John

I meant still bootstrap it from the end.

Hmm, I thought this is exactly the kind of work you like, all analog :-)

I know, that's what your sim shows. This is why I think it is important to get the most clean high-BW amp solution possible. And I just don't think that's easily possible with a CFB running at G=+1. They are like a car with worn shocks.

But I think first the root cause for the weird 100MHz ring-a-ding-ding has to be found. Can't imagine an AD8014 doing that on its own.

them

With 1K, the recommended datasheet value, it doesn't ring, but it has a high slope from zero to about +1.3 volts or so, then settles down to follow the cap. The initial slope is about twice the correct value.

I tried 470 ohms, and it's a compromise: a little ringing, a little pre-slope. The equivalent ramp error is about 75 ps RMS, so I may live with that. Still ugly, though.

John

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In your sim file it stops doing the overshoot when the gain is above 1.3 but who knows, SPICE models only go so far.

Looks like you need a faster amp. How about this one?

Assuming cost is not of prime concern here.

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We have THS3201s (1.8 GHz) and AD8009s (1 GHz) in stock, so I'll have to try them some day. But I'm down to 75 ps with the AD8014 and 470 ohms, so I think I'll rest there for a while.

Too bad about the sims.

John

Yes, ok but still, have you tried a load R directly on the CA output ?

Jamie

The AD8014 Spice model is crap... pure behavioral. Even the NPN and PNP used in the model are Spice defaults. ...Jim Thompson

But it doesn't behave right!

John