A 1.5V to (1.5V -> 6.5V) level shifter, and vice versa

Basically, my boss wants me to build a testing system for an IC, which has an absolute maximum rating of 1.5V to 6.5V VCC.

So my boss wants me to apply some digital signals to the IC and read some feedback (at up to 20MHz clock). With a variable VCC from 1.5V to 6.5V (and other features besides, such as being low power). And I need to be able to apply 1.5V to 6.5V voltage at high, based on my current VCC.

However the only level shifters I've found are either 1.5V to 5.5V supply voltages or 4V to very high supply voltages. Nothing quite fits the 1.5V to 6.5V range.

The best I've managed to come up with is to use a bunch of (mechanical) relays to select between two level shifters, one for 1.5V to 5.5V range, the other for 5.5V to 6.5V range. I'm not sure if solid-state relays will work, because I'm almost sure that the propagation delay of actual metal is much faster than propagation delay of semiconductor.

Is this the best solution? Might I have missed a level shifter capable of reaching the required range?

My controlling device is an FPGA, which can have a VOH of 1.2V, 1.5V,

3.0V and 3.3V (1.5V and 3.3V being the preferred, because our FPGA prototyping board has only those voltages). The maximum recommended VIH for the FPGA is 4.1V, with the minimum obviously varying according to the I/O VCC I select.

Thanks in advance!

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Brendan Gillatt

Brendan Gillatt wrote in news: snipped-for-privacy@pipex.net:

Sometimes an input might be driven with a voltage reaching or exceeding the supply voltage, If you have to test this condition, you need two variables, your supply, and your pullup voltage.

Once you have those it's easy with the method I copy from an old post of mine (idea raided from a 'Best of EDN' book I found).

Try an n-channel JFET, gate to common ground, pull-up voltage through resistor on the drain, input to the source. Anything over 1 to 2V input should be fine. Without having seen your circuit I can't be sure, but this might all be doable with a single FET per input. I'm not sure how low your pullup voltage can go but if the FET is satisfied, you could offset the final voltage the inputs see by passing through one or more signal diodes between FET drain and input. You'd then have a continuously variable range to test by adjusting the main pullup supplie's voltage.

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Lostgallifreyan wrote in news:Xns99BCA587377AFzoodlewurdle@

Note to self: If I ever make a typo that tasteless again I'll shoot myself, I swear. >:)

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