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ldo's opamp problem

: i think it should be the same for higher vdd but it is not. : opamp's gain is lower for lower IL than for higher IL. : for higher vdd neither device goes to linear, even for higher load : current demand. so where does it come from?

Right, those results make sense to me. For higher vdd, you get:

  1. Higher Vgs for the same Vg on the output pass device. Thus, the output of the opamp doesn't need to be pulled as low to provide the higher Vgs drive to provide the higher load current. This increases the minimum output voltage of your opamp, which results in higher Vds across the load (which you call output) devices of your opamp.
  2. As long as all devices stay in sat. the gain of your opamp should remain relatively constant. The gain of the pass device, however, will increase with increasing load current, so therefore, the overall gain of the regulator MIGHT slightly increase with increasing load current. I say "might" because, the gm of the output device increases proportionally to the square root of its drain current. If you are driving a purely resistive load, the greater load current is caused because of a smaller (output) impedance. Therefore, although gm increases, Rout decreases more, so the output stage gain ~ gm*Rout will decrease. If your load is not purely resistive, then things depend upon the spectrum of your load current, so the output stage gain may actually increase.

What is the difference in gain that you are observing for the cases where all transistors remain in saturation? If it is "small" it may be due to some second order effect.

Joe

Reply to
<jwelser
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[snip]

Look at the pass device characteristic curves. For a VDS drop less than approximately VT you will be in the "linear" region" irrespective of load current.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.
Reply to
Jim Thompson

: Look at the pass device characteristic curves. For a VDS drop less : than approximately VT you will be in the "linear" region" irrespective : of load current.

Not true. Vds must be greater than (Vgs - Vt) for a device to be saturated. Vgs - Vt is often less than Vt in low voltage (or any, for that matter) designs. This fact represents an advantage of "Wide-Swing" Cascode Current Mirrors over "Normal" Cascode Current Mirrors, for example. Joe

Reply to
<jwelser

thank you very much for clear explanation

if you'd be so kind, please consider this problem.

my LDO should be designed for low power loss.

the low current opamp's output resistance is huge as huge is also power device input capacity. This causes that pole related to this values is very low so the UGF is low.

I meet the specifications only is i bias the opamp with high quiescent current.

To avoid it i need a buffer, but what can i use for such a low vdd as

1.3V? this buffer should drive power device properly.

i used one stage nmos or pmos ota in the buffer configuration but once nmos input devices are cutoff and buffer present high resistance, the other time pmos is cutoff.

could you recommend any architectures? maybe class AB or some kind of adaptive biasing?

regards

Reply to
jutek

The OP is passing "substantial" power, he's not near cut-off.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.
Reply to
Jim Thompson

: The OP is passing "substantial" power, he's not near cut-off.

Apples and oranges. Cutoff = Vgs < Vt. Linear = Vds < (Vgs - Vt)

You said Linear = Vds < Vt

Not true, and not related to cutoff. Am I misunderstanding something?

Joe

Reply to
<jwelser

No. Just my rule-of-thumb. But for low VGS you ARE at LOW current. Theory is nice, practice is a bitch ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.
Reply to
Jim Thompson

: No. Just my rule-of-thumb. But for low VGS you ARE at LOW current. : Theory is nice, practice is a bitch ;-)

So what you are saying is that you look for Vgs >= 2Vt (i.e. Vgs

- Vt >= Vt) for a device to be passing "substantial" current in saturation? IMHO, that's not necessarily a good rule-of-thumb for low-voltage design (what we are talking about here) where you are even lucky if Vdd >= 2Vt (in theory or practice -- Vt ~ 600 mV, Vdd = 1.3V barely works with your rule of thumb.)

Also, devices passing large current need not have large Vgs. They can also be big. For a low-voltage design, this is often the only (if less desirable, Since I vs. W/L is only linear) solution.

Joe

Reply to
<jwelser

: could you recommend any architectures? : maybe class AB or some kind of adaptive biasing?

I understand your problem. Because of the large output pass device, the dominant pole of your regulator is due to your first stage (input pair) gm divided by the large gate cap of the output pass device, rather than the output gm on Cload. Presumably your poles are not widely spaced and you can have stability problems. To solve this, you can increase your opamp bias current, increase the first stage gm, and move the first stage pole past that of the second stage.

First off, have you tried Miller Compensating the opamp.? It's not typically done with voltage regulators, but if you don't need the bandwidth (which you typically don't for a voltage regulator) there is no reason why it wouldn't work.

Your approach of using a buffer isn't necessarily bad, it's just more difficult to keep stable. You are essentially adding an additional stage to your opamp, which you'll then have to compensate using nested Miller compensation or something else. Compensating multi-stage opamps can be tricky, but, more importantly, stable multi-stage opamps usually have a lower bandwidth than 2-stage amps, so if you were trying to get bandwidth by using a multi-stage amp, that won't work.

Using a class-AB first stage is an interesting idea that I have never seriously pursued. It will solve your current/power problems, but your input stage pole will also move with the [changing] input stage bias current. My instinct is that it wouldn't necessarily solve your bandwidth/stability problems, but it might be worth looking into. I always wind up running into the classic class-AB input stage somewhere when I flip through my textbooks, so it is probably in either the Johns, Martin book, or Razavi's book.

Good Luck,

Joe

Reply to
<jwelser

The processes I work on may have a library containing 5V, 3.3V, 2.5V and 1.8V or even 1.3V devices... 4nm < tox < 13.3nm, 0.32V < VTHO <

0.78V.

From experience I try to use the smallest device that will pass the worst-case load over temperature and process corners.

My typical LDO's...

3.3V In => 2.5V Out

2.5V In => 1.8V or 1.3V Out

Nominal Inputs shown, but 3.3V can actually often be worst-cased to

3.0V or even 2.7V

And have lousy rejection of noise on VDD. Exacerbated by the low loop bandwidth forced by having to stay stable with a wide variety of input voltage range and output load current.

In MY real world the pass device can be in the linear OR saturation region, making life a true bitch ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.
Reply to
Jim Thompson

: The processes I work on may have a library containing 5V, 3.3V, 2.5V : and 1.8V or even 1.3V devices... 4nm < tox < 13.3nm, 0.32V < VTHO < : 0.78V.

: From experience I try to use the smallest device that will pass the : worst-case load over temperature and process corners.

Fair enough. I usually try to avoid real low-Vt devices (because of high leakage) and I don't often get to have multiple thin-ox devices (because of $$$).

: My typical LDO's...

: 3.3V In => 2.5V Out

: 2.5V In => 1.8V or 1.3V Out

Fine, but this one is 1.3V In => 0.8V Out (If I remember correctly.) Vds = 0.5V, limiting Vdsat_max to about 0.4V.

: And have lousy rejection of noise on VDD. Exacerbated by the low loop : bandwidth forced by having to stay stable with a wide variety of input : voltage range and output load current.

You'll have to explain this one. PSRR is limited only by gds for a device in sat. (assume the pass device remains in sat.) gds = lambda*Id, and lambda is inversely proportional to L ONLY. Whether you increase Id with a higher (Vgs - Vt) or higher W (I assume minimum length for the output pass device) doesn't change your gds.

: In MY real world the pass device can be in the linear OR saturation : region, making life a true bitch ;-)

Why would you let the pass device go into the linear region if you cared about PSRR? Devices in the linear region have a large gds, and, therefore, crappy/no PSRR.

Joe

Reply to
<jwelser

i think you meant GBW is gm/Cpass cause the pole is 1/(2pi*rout*Cpass)

Presumably your poles are not widely

the problem is i can't increase bias current cause LDO should as low quiescent current as possible

i have seen such a solution, but i'll design it later. for now i want to use one stage opamp, to avoid compensation problems. i tried simple OTA, mirrored OTA, folded cascode. it would be enough if i use buffer. but the buffer is now a problem. source followers (n or p type) are not enough for vdd=1.3V

BTW if i use two stage miller opamp and thereafter split its poles, the one will go to lower frequencies and will be close enough to the LDO domain pole consisted of Cload and LDO output resistance. So i will also have stability problems, but worse the UGF will be smaller so LDO will be slower and load and line regulation will be worse. I need UGF about 1Mhz

Reply to
jutek

[snip]
[snip]

Aaaah! What I wouldn't give for a world as simplistic as seen from the academic view.

Try VDD ripple at 1GHz, then re-visit "PSRR is limited only by gds for a device in sat".

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.
Reply to
Jim Thompson

: Aaaah! What I wouldn't give for a world as simplistic as seen from : the academic view.

What's with this snide comment? Oh, because I use my UT (personal) email account, I necessarily have an academic view? If I posted from my work email, would that make things different?

: Try VDD ripple at 1GHz, then re-visit "PSRR is limited only by gds for : a device in sat".

You're jumping all over the place, with no point. How does this relate to anything that you've said in the past? Your statement above is still wrong. At 1 GHz, the PSRR is STILL limited by gds, it's just that the capacitive component of gds (potentially) matters more than the conductive component. This all started with your WRONG comment that a MOS device enters the linear region when its Vds < Vt. Now you've buried yourself in so much crap that you can't get out and you're resorting to personal attacks ("You must be wrong because you are an academic," which is wrong on both counts -- I am not an academic and I'm not wrong until you at least explain why.)

I'm interested in hearing you explain yourself, not in snide comments. If you have a valid point, I'll listen and learn. If you can only provide snide comments, then please don't bother to respond at all.

Joe

Reply to
<jwelser

I was simply trying to make the point that a larger device WILL NOT improve/suffice in many real-world situations (like PLL synthesizers), particularly the situations I am in... regulators for low-voltage "core" devices.

I still stand by my "rule-of-thumb" as a realistic approach (at least for me) because I must cope with loads that range from nearly zero up to AMPS, so I go for (what I consider) worst-case.

Sorry if I offended you.

When I see a (possible) academic I'm reminded of Win... make a subcircuit patch for the Level=3 MOSFEET model, rather than doing it right with Level=7/49 ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.
Reply to
Jim Thompson

: I was simply trying to make the point that a larger device WILL NOT : improve/suffice in many real-world situations (like PLL synthesizers), : particularly the situations I am in... regulators for low-voltage : "core" devices.

Every application is different. Personally, I probably wouldn't (and haven't) use a series regulator if I wanted a high bandwidth regulator for a synth. (I've designed those too.) I'll define High bandwidth = High Frequency Current is provided by the regulator itself, not some external cap.

Based upon your previous post, it doesn't seem like you've been involved in Low Voltage Design (Which I'll loosely define as Vdd < 2Vt). There are a completely different set of "rules," where all of your rules of thumb go out the window. That's why I prefer to stick with the basics

-- They'll get you most of the way regardless of the situation.

Let's once again look at this specific example (form the OP):

Vdd = 1.3V (min) Vreg = 0.8V Iload (max) = 100 mA

By the spec., Vds_max = 0.5V, and realistically, Vdsat_max =

0.4V. This pretty much sets the size of the output device in stone (W/L = 41667, for K' = 30 uA/V^2 -- NOTE TO OP, you might want to make sure that your output device is that large, or adjust if your K' differs substantially from my assumption) There is simply no way to make this smaller with ANY type of device (and have your output pass device remain in sat. over all load conditions.) Using a low-Vt device isn't going to get you out of this one -- it's just going to get you lots of leakage from that device. If you insist upon using one just so that your rule-of-thumb stands, you'll wind up solving nothing and creating more problems for yourself.

I'll grant you that this regulator wouldn't be anywhere near suitable for high-bandwidth applications, but there's just no way that you could design a series regulator that is (see my comment above) so I never assumed that we were talking about a high-bandwidth application here.

: I still stand by my "rule-of-thumb" as a realistic approach (at least : for me) because I must cope with loads that range from nearly zero up : to AMPS, so I go for (what I consider) worst-case.

I still disagree (see above,) but I'm likely not going to convince you to change your mind over the Internet :) : Sorry if I offended you.

Apology accepted.

: When I see a (possible) academic I'm reminded of Win... make a : subcircuit patch for the Level=3 MOSFEET model, rather than doing it : right with Level=7/49 ;-)

I'm not familiar with that situation, but I think that even Universities use Level 49 models nowadays (doesn't MOSIS provide level 49 models?) but I'm not positive.

Joe

Reply to
<jwelser

: BTW if i use two stage miller opamp and thereafter split its poles, the : one will go to lower frequencies and will be close enough to the LDO : domain pole consisted of Cload and LDO output resistance. So i will also : have stability problems, but worse the UGF will be smaller so LDO will : be slower and load and line regulation will be worse. I need UGF about 1Mhz

I misunderstood what you said in your last post. I thought you were saying that your dominant pole was the pole created by your input stage.

I don't have many more suggestions, I'm afraid. Try to get your input stage gm up as high as possible. If your input diff. pair devices aren't already in weak inversion, size them so that they are. If you have native or low-Vt devices at your disposal, use them for your input diff. pair. Other than that, there aren't many things that you can do. If you add a buffer, you have essentially added another stage, and need to compensate the entire regulator like you would a 3-stage opamp.

Good Luck,

Joe

Reply to
<jwelser

I have done some shunt regulator designs to get better PSRR.

Only logic, at least in CMOS... but I've done 1V hearing aids in bipolar.

I'm rarely troubled by theory ;-)

Again, I'm rarely troubled by theory ;-)

Yep. But the discrete power-MOS crowd is lagging way behind.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.
Reply to
Jim Thompson

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