Laugh of the Day

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Nice current limit... until Q2 goes into second breakdown, dies and still kills R2. Foldback current limiting would be better.

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

I don't know which I got the bigger laugh over, the circuit or the fact that it was from a guy that worked at Tata Motors. Just the thought of motorized tatas brought a smile to my face...

Aw, be nice. It's only 10mA. Tata probably still makes their ECUs from a few dozen TO-92 transistors and through-the-hole passives.

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What I was driving at was that particular configuration has been in use literally forever.

I thought they had a runt in the trunk twiddling pots :-) ...Jim Thompson

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An ECU wallah?

Can't reach it. Bad redirect.

Here's the schematic from the page. I had the same problem as you, but finally got there.

Ed

+-------> Buffered signal | output Internal /c signal >--[R1]---+----| Q2 NPN input | \e +-----+ | | | Transistor Q1 restricts the current c\ | through open-collector driver Q2 Q1 NPN |----------+ by limiting the voltage across R2 e/ | to about 700 mV, protecting Q2 | [R2] against high-voltage shorts. | | +------------+ | Gnd

...pretty damned obvious stuff, for a publication with an intended audience of design engineers. Not too useful in most cases, either.

I'd wager that fewer than 1 in 5 newly-minted BSEEs could come up with such a circuit today... whereas probably at at least 4 of 5 could when you graduated? :-)

Yes.

---Joel

Article points out how they save R2 from destruction, by keeping it small. :-) But poor Q2, overheating until its death by a short. They'll be needing the fuse block.

Now, if they'd added foldback current limiting ...

. ,--------+-------> Buffered signal . | | output . Input | |/c . >-- R1 --+--- | -----| Q2 NPN . | | |\e . | R4 | . c\| | | . Q1 NPN |--+-- R3 --+ . e/| | . | R2 . | | . '-------------+ . | . Gnd

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 Thanks,
    - Win

Likely fewer than one in five will ever be design engineers, particularly at the transistor level. _Electronic_Design_ is *supposed* to be for that one, though.

"that one" obviously was *not you*.

AlwaysWrong, the night janitor at the sewage treatment plant, is *always* wrong.

I think I follow this. R3+R4 is a voltage divider across Q2's Vce. Normally, when Q2 is on, it's output should be fairly low and R3's division of Vce is close to nil, so R2 works as intended. However, if Vce is large while Q2 is on (shorted collector?) then the R3 division of Vce stacks on R2, lowering R2's portion of the designed limit and causing Q2's Ic to be forced to drop down. If Q2 is off, then R2's drop should be nil, leaving Q2's "off" Vce entirely across R4+R3. So one must make sure that R3's division ratio in the Q2-off case isn't enough to turn Q1 on. Say 0.2V or so out of the given designed rail for the open collector output?

What about a 'speed up' cap across R1? 100pF or so?

Jon

At least they let him swim in the vat, to satisfy his fetish.

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