Larkin should like The Unix Haters Handbook

Cool; I'll make time to read that soon.

We just hired our first official Software Engineer (we aren't allowed to call him a programmer) for this Linux box we're doing.

So we got the PLX demo board (for their PCIe interface chip) and their Linux drivers. The drivers don't work, of course. So, in time-honored fashion, we are now recompiling both the driver *and* the Linux kernel, together, to try to resolve the incompatibilities.

Yup. After about a man-month (which is about 250 hours in this biz) it's mostly working. I don't often spend that sort of time on an entire, bare-metal embedded product.

John

Perhaps hire someone better. At a previous employer we hired a real Linux expert. A driver for 'our' PCI card only took him 2 or 3 days.

Lately I have been doing a lot of Linux kernel hacking myself for a product which uses Linux on an embedded and I must say most stuff in the Linux kernel is pretty straightforward.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn\'t fit, use a bigger hammer!"
--------------------------------------------------------------

They don't get much better than this guy. Trust me on that.

But the PLX chip isn't. The "data sheet" is a 592 page PDF file.

Interfacing the dram (135 pages) to the FPGA (206 pages) should be relatively easy, based on total page count.

John

Nobody is perfect... Perhaps it takes a more hardware oriented guy. The Linux guru I worked with connected the parallel port to an Agilent MSO. He used that to debug the driver in realtime by writing state information to the printer port. The ability to load/unload a Linux kernel driver makes it possible to have very short turn-around times. No need to recompile the entire kernel or reboot the machine. It just shouldn't take that long to get a driver up and running.

Depends on the writers. Infineon (formely Siemens) can spend over 300 pages on what Zarlink (formerly Mitel) can explain using only 20 pages. Both describing similar chips.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn\'t fit, use a bigger hammer!"
--------------------------------------------------------------

On a sunny day (Fri, 05 Jun 2009 21:09:26 GMT) it happened snipped-for-privacy@puntnl.niks (Nico Coesel) wrote in :

That is true, but if your module hangs, then you will need to reboot....

Indeed.

What is a 'PLX' chip?

e

ions

=A0I

efuse

Why aren't you allowed to call him a programmer?

Michael

We're using this one:

There's actually two chips in the package, a PCIe-to-PCI bridge, and a PCI-to-local-bus sort of thing. We're using it to go from an embedded PC to an FPGA on our board.

John

Because he doesn't want us to.

That's fine; titles are the cheapest thing we have.

John

Yep, they are in small companies (they asked me what I wanted on my business cards). Titles are important in large companies though. Lawyers have seen to that.

The two bridges in that package even have different core supply voltages. I asked the local PLX rep about a better integrated solution that used the same supply voltage throughout, and he swore that the '8311 was monolithic. I don't think he understood the question though.

Cascaded bridges hurt throughput for random accesses, as the access time is determined by the latency (which will increase when you have two bridges). It shouldn't matter much for streaming data though.

Regards, Allan

At 66 MHz, doing 32-bit DMA transfers, it seems to do something like

32 transfers, rest for 8 clocks, 32 transfers, etc. So it averages about 56 MHz x 32 bits. Our ADC will do 64 Ms/s max, 16 bit data, so it's sort of OK. We'll do a bit of FIFO in the FPGA to smooth things out.

The Gennum chip is four lanes (PLX is only one) so should scream. But it requires a lot of the DMA logic to be in the FPGA, and they are still promising Linux drivers some day... tempting but too risky.

John

This one looks even better, but I'm not sure I'd want to use it without an English language data sheet:

aaeb04.html PCIe x4 lanes, 2xDMA, DDR SDRAM controller (presumably for DMA buffers),

2x I2C controllers, SPI, 8x GPIO, FPGA configuration logic, serial port, 64 bit / 133MHz local bus.

I found a product brief in English here:

2008.pdf

Regards, Allan

Oops.

These links should be more clickable now that I've turned wrap off:

Regards, Allan

Yes... but that would only happen a few times. When using the parallel port (or GPIO) debugging you can see exactly where it hangs.

A 'PLX chip' is short for a range of chips made by PLX to offer a simple (ISA like if you want) interface to a PCI or PCI express bus. These chips are more or less industry standard. For low and mid volume products it makes no sense to put a PCI express or PCI core into an FPGA.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn\'t fit, use a bigger hammer!"
--------------------------------------------------------------

On a sunny day (Sat, 06 Jun 2009 08:35:01 GMT) it happened snipped-for-privacy@puntnl.niks (Nico Coesel) wrote in :

OK, thanks.

On a sunny day (Fri, 05 Jun 2009 16:17:07 -0700) it happened John Larkin wrote in :

337 pins.. sigh. :-)

OK I was sort of hoping that by now we would have gigabit serial, possibly optical, links.....

Drivers are quite sensitive to the kernel version. While userspace only cares about 2.4 versus 2.6, drivers will often care about 2.6.26 versus

2.6.27, and occasionally care about 2.6.27.9 versus 2.6.27.10 (the latter shouldn't happen, but nobody's perfect).

672 pins! Yikes!

John

PCI express is gigabit serial. So is gb Ethernet. And both are wicked complex.

John