Large capacitance varicaps, where are thee?

Yes, and on the simulator everything went to pots when I did. Now I don;'t know how the real part behaves because I don't have one and got no time for elaborate tests. So I'll just use a mux and a bunch of caps.

Sure. Use Coss (G-S shorted) which usually is highly non linear and has a low enough esr in the 10s to 100s of mR.

The figures you need are harder to find because the process have improved a lot, but still, poking a bit leads for example to:

Now, you can also do something entirely different like:

| | +--------------. | | --- | --- | | | | | | | +5V Tune >-----. +-----. | V | | | | | .-. | | | .-. 10K/4K7 | | \| | |/ | | | | Q1 |---+------| Q2 | |22K '-' '-' | | - | | +------+ ^ +------+ | | | | | | 100R.-. | .-. | 100n --- | | === | | --- 100n --- | | GND 100R| | --- | '-' '-' | | | | | === === === === GND GND GND GND

With a dual BJT and a low enough cap (to compensate for the BJTs offset) you might save the Q2 emitter bias components. You might even want to further lower the cap value since you have available gain.

Thanks, that FET idea is a good one, should be possible to find one that has the kink at lower more civilized voltages. It might be a bit drifty with temperature though and that would not be so cool for my case.

Everything is single sourced now so that's an irrelevant argument.

Almost all do. Everything I've used is current-mode.

You trust behaviorals? Amazing.

Interestingly, that's what I tried a few days ago and it didnt' work. Now it does, no funny waveforms. Hmm ...

I thought you had feedback, so you should not have pb.

For the tempco I don't expect it to be any different from a varicap. Now you have the production spread to cope with. It'll almost surely be wider than a varicap which is done for that.

Anyway the spread given in the datasheet between typical and Abs max is a 3:2 ratio to the nth decimal place, so I'd expect it to be much better ( much like the high leakage current of CMOS gate).

Anyone having a better informed figure for the actual power MOSFETs capacitance spread?

Why did you then flag the single source issue if you think it's irrelevant?

For some of my clients this is relevant. I have used PWM chips in the past that are 2nd-sourced. From Richtek and TI, for example. But those tend to be older designs.

I am replacing a TI regulator that isn't, and this is one of the reasons.

Depends on who made them. From Linear Technology, yes, usually I trust them. Many years of successful design with their models gives me confidence.

Where is the sawtooth located? Minimum trough voltage? Supply voltage(s)? ...Jim Thompson

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frequency

At the timing pin CT, where the timing cap hangs off of.

The voltage swing is zero at start of ramp, ramps up to 2.3V, where it is being quite brutally reset by discharging the cap, about 50mA. Now it starts to ramp up again. So I guess they have a comparator in there that sense when 2.3V is reached.

The Supply voltage for that part is either about 9V or 5V (they don't say, internal to the chip)

Yes, but it has to let go for extended periods of time.

What good is that? So the board doesn't work like the simulation. Is the manufacturer going to fix the chip? They might fix the model and you still miss your schedule.

Rick

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You *could* just add to, or fight, their current source.

The brutal discharge makes cap multipliers difficult. I think you're stuck with (digitally) switching caps in and out.

What is the ramp-up time? I gather that is the variable part to match your resonant load?

An alternative would be to change the comparator threshold... if you can get to it.

Is this adjustment on the fly, or is it set once and forget? ...Jim Thompson

Helluva good idea! Since it's a timer and not particularly linearity sensitive you could use a bipolar mirror. ...Jim Thompson

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Hmmm, just put in the cap for the highest frequency, and sink some charging current to pull the frequency down. Sounds like a DAC of some sort, and maybe as simple a sink as an NPN with an emitter resistor. Of course, you have to disappear 5/8 of the ramp current to cover your stated frequency range.

The other direction, adding current to push the frequency up, is numerically safer. You should be able to compute the existing charging current pretty easily... or measure it... to see if that looks safe.

Heck, an opamp swinging from 0 to, say, +10, and a resistor to the cap node, would probably do it. That can add a lot of current and remove a little, a nice compromise.

Or, given the "brutal discharge", and it's comparator-tripped, just add pull-up current to vary the timing. Then you don't have headroom issues on the mirror. ...Jim Thompson

capacitance

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Looks like a current source (not sink) will work, for some strange reason it didn't last week. But LTC would have to bless this, to avoid some unforeseen pathology in there.

Or current sourcing, if LTC blesses that. Pronlem ist, my main guy is on a seminar all week and I'd need to know this week. They are really good when it comes to support though.

Nope, can't, and the slope is used elsewhere like for slope compensation to avoid the possible RHP zero buckaroo. So if you truncate it too much other things can go kaputt.

Sometimes on the fly, then pauses during certain phases of the game, then comes back to regulate.

oo

pin

I wonder what that strange ramping up current sink at the end of each cycles is?

-Lasse