JFETs and "pinch-off" - two meanings?

Like all contradictory terms, either both are correct or neither. Insisting on one or the other just starts a religious war.

I prefer your former definition, but that's because it's what I learned in school. Then again, when I was in school I thought it was misleading...

Hello Bill,

The latter, sez Winfield Hill in "The Art of Electronics". And he ought to know :-)

Regards, Joerg

Which one "pinches off" the current?

The flat (high drain impedance) region is known as the saturation region, because the current is saturated and won't increase with more Vds. The linear region is usually under a half volt or so (depending on transistor), where current increases in proportion to gate and drain voltages. (This is confusingly opposite the terminology used for bipolar transistors, where the "switch" is "saturated" in the low-voltage region, and the high-impedance region is called "linear" because a linear amplifier operates in that region.)

At least that's what I remember. I would just as soon call the high-impedance region on all transistors the linear region and the other for saturation, just for simplicity.

Tim

-- Deep Fryer: a very philosophical monk. Website:

Same here, I grew up with BJT's ;-)

...Jim Thompson

Oh, but one is _current_ saturated and the other is _voltage_ saturated. Is it obvious now? :)

Thanks guys -- I very much appreciate the help. I guess, for whatever weird reason, "pinch-off" has two separate meanings when talking about JFETs! Talk about confusing!!! (I wonder how this all came about?).

Thanks Again,

-Bill

Did I say that? Pinch off is a gate-voltage definition. It's one of two things: the gate voltage the manufacturer specifies, e.g. Vgs(off) at Id = 1nA, 10nA, 10uA, 250uA, etc., or better, the gate voltage Vth where the extrapolated sqrt Id vs Vgs plot goes through zero (AoE figure 3.13, page 122). While you won't get the latter parameter from a datasheet, any JFET will beautifully provide the data for a textbook extrapolated sqrt-Id plot. Sadly the data from next JFET in the batch likely won't very closely match that plot; the rule will be the same but its extrapolated Vth voltage will be different.

They are one and the same. The pinch-off voltage of a JFET, Vp, is a function of the doping profile and physical dimensions of the device design. The physics governing device operation is such that the device saturation region current is controlled by the ratio of the applied Vgs to Vp according to Ids,sat=Idss*(1-Vgs/Vp)^2, and Vds=Vgs-Vp is the minimum drain source voltage at which this occurs.

pinch-off is when the jFet has been reversed bias enough to place it in it's highest resistance state between the drain and source. Jfets have a natural forward bias on them to start with. jFets conduct naturally, reverse bias is required on the gate to get the DS to its highest state of off resistance, this is what the pinch-off voltage which is Vgs..

that is the closest i can explain it.

Hi, this is a real confusion i had in my engg school too.to rectify myself i used to rely on the fact not on the terminology.i would suggest you to understand the matter as the channel pinch-off(first one) & the later one as gate pinch-off.

hope you could catch my point to negate your confusion.

Baps

Bill, Manufacturer's data sheets specify pinchoff (cutoff) voltage as the Vgs necessary to reduce the drain current to a specified level, with a specified Vds applied. See, for example, the spec sheet for the 2N4392.

Hello Win,

I believe you did, AoE page 120, the paragraph under figure 3.11. "For JFETs the gate-source voltage at which drain current approaches zero is called...".

But I agree, what is considered close enough to zero varies from mfg to mfg and might even be influenced by their marketeers. I wish there was some kind of standard, like x many dB under abs max current or something. Then again, as you said, the lot variations are so huge that it wouldn't make much sense to nail V pinch-off down to within a few hundred mV.

Regards, Joerg

actually both r correct

since effect can b explained using gate voltage and Vds