Back to back Jfets

A while ago Phil Hobbs mentioned a jfet with 'interchangeable' drain and source. I am wondering how much different that would be compared to if you got 2 jfets (call them Q1 and Q2) and connected Q1 source to Q2 drain and Q1 drain to Q2 source while commoning the gates together?

Any thoughts?

Reply to
David Eather
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Regular J-FETs are perfectly symmetrical. The "drain" is the positive end o f the channel, and the "source" the negative end. Swap the polarity and the J-FET works just the same way as it did before.

The gate cut-off voltage varies a lot from FET to FET - even with nominally identical devices - so what you propose is equivalent to connecting two ra ndom J-FETs in parallel. Under most circumstance most of the current is goi ng to flow through just one of the devices, and the second part will just a dd stray capacitance.

You can (or a least could) buy monolithic matched pairs of J-FETs, where th e channels tended to be adjacent serpentine stripes on the same wafer of si licon, and these could have fairly closely matched gate-cutoff voltages.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

JFETs are depletion devices, which all work fine around I_DSS (i.e. zero volts gate-source). So unless you're working at very low drain current, parallelling two of them is pretty nearly equivalent to using twice as big a FET. (There are some asymmetrical JFETs, in which case this isn't quite the case, but they'll all be conducting heavily at zero volts bias.)

The only JFET I use with any regularity is the BF862, and I routinely parallel them up to get higher transconductance and lower noise. Their gate-drain capacitance is a few pF, so with high capacitance transducers such as big photodiodes, you win SNR until the FET capacitance starts to dominate.

With an I_DSS range of 10 to 25 mA, that costs a lot of power, of course, so usually do you don't go quite that far. I've used as many as

10 of them, directly parallelled.

Cheers

Phil Hobbs

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Reply to
Phil Hobbs

If you maintain a (sufficient) voltage across the JFETs (as you would have in a cascode, for example), each one will run at its own Idss, which is fairly closely matched (maybe 2:1).

That's how you can parallel a metric crapload of JFETs and get sqrt(metric crapload) (ideally, anyway) improvement in noise performance.

Paralleling two (upside down or rightside up) will give a improvement in noise of as much as 41% for double the current.

Reply to
Spehro Pefhany

Somebody pointed me to an online copy of the National Semiconductor JFET manual a while ago... it has actual diagrams of the layouts of the dice for many of their JFET transistors. What I wrote at the time:

For what it's worth... in the National Semiconductor book Bill pointed me to, only one of the N-JFET processes (#52) explicitly states that the source and drain are interchangeable.

In every one of those processes that I looked at (I think) it appears that there is at least some asymmetry in the geometry of the source and drain conductors on the dice. They're laid out as interlacing "fingers", and it seems to be the case that one or the other of the terminals has one more "finger" to it (that is, its outermost fingers are always "outside" of the outermost fingers of the other terminal). Most commonly it's the source which has the extra finger.

This could mean that this terminal has a bit of additional channel area around it (on the "outside"). This might result in a slight difference in channel-narrowing and pinch-off behavior between the two possible orientations of the JFET (e.g. source-as-source, or source-used-as-drain).

I'd hazard a guess that this is probably so slight that it's quite a bit less than the part-to-part variation to be expected between different JFETs of the same part number (or even from the same wafer). I suppose it might be noticeable if you had a monolithic dual, and ran one of the two right-side-up and the other upside-down... but that'd be a silly way to spend your money :-)

I suppose I could put a few different ones on a curve-tracer and see whether reversing the source/drain makes a significant difference.

I never did do that particular experiment... but since I've gotten a

7CT1N plug-in for my old 7904 scope, and have made a nice socketed test-jig for it, I really should run one or two JFETs through a test of this sort and take photos of the screen and see if the curves vary at all when I flip the transistor upside-down.
Reply to
David Platt

Yes, but the price is ex$$$pensive!

Reply to
Robert Baer

Yes.

Ahmmm.... well, you have been very, very, lucky then. As Bill said, Vt tolerances are relatively huge. Typically more than a 1V. Some data sheets quote 3V.

Indeed, running at 0V gate source is worse than running with a source resister to generate self bias.

Just a +/- 10% on a 2V Vt at vgs=0V might get you 20%, and 10% for self bias.

I just just don't see it as viable to parallel jfets for reliable main stream production, your goanna get 3:1 ratios in current.

Kevin Aylward

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Reply to
Kevin Aylward

No luck is involved, and you clearly have no idea of the application.

The I_DSS range of the BF862 is 2.5:1, and its transconductance is so high that all the action is over in 400 mV of V_GS.

BF862s can be run slightly enhanced, which reduces their flatband noise a bit and increases their transconductance, but of course increases the gate leakage. Sometimes that's a win, sometimes not.

Servoing them to run at I_DSS optimizes the performance of each given FET for bootstrap service, regardless of the I_DSS distribution. The key metric of a bootstrap is how close its (loaded) gain is to (1.000000

  • j 0.0000000), so I don't need any particular value of I_DSS.

If I were building resistance-coupled audio preamps, I wouldn't be using a JFET, for sure.

Cheers

Phil Hobbs

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Reply to
Phil Hobbs

On a sunny day (Fri, 14 Nov 2014 09:54:36 -0500) it happened Phil Hobbs wrote in :

I have seen, and used myself, JFETs as AGC element in audio mixers. One applictation I have seen is where the DJ screams (speaks) into the mike, then the music level is automagically reduced.

With a voltage divider on the gate it is sort of a resistor:

----------------- + | | R2 |-- d |-||----->| JFET R3 C2 | |-- s | R4 | | | |

---R1 --||---------)--------- audio out audio C1 | in volume control voltage

The JFET shorts the audio against the + supply line (that must be decoupled). The volume control is between ground and some positive voltage, the moee positive the less audio comes out.

The ratio R2 / R3 is to make a good resistor... C1, C2 are simply coupling caps for audio

R1 is what the circuit works against.

R4 is a very high value.

JFETs are cool.

Reply to
Jan Panteltje

The 50% gate feedback trick works pretty well for JFET variable resistors, but interestingly not for MOSFETs. I took some data on that one time, looking to see how well 2N7002s linearized. 50% had little effect, but somewhere between 150% and 200% worked pretty well. I put two of them in series, with their gates connected together, and took about 90% feedback from the top drain to the two gates. THD improved about 20 dB compared with a single device at the same resistance.

(This was down in the 2-10 ohm range.)

Cheers

Phil Hobbs

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Reply to
Phil Hobbs

Many thanks all!

Reply to
David Eather

I don't know your exact circuit. However, I do know about jfets.

I don't know your exact circuit.

Either you are putting them, as you actually claimed, in direct parallel, i.e. gate to gate, source to source, drain to drain, or you are driving them separately, e.g. individual current setting sources.

If they are in parallel as you claimed, they wont match. Period. They will run at vastly different currents. With typical manufacturing specs of several volts of Vt variations, some devices will be fully off, with the other taking all the current. Period.

Hint: Go and run a SuperSpice test circuit and set one Vt to -1V and another to -3V, which is way within typically variation specs for jfets. Typically a

10:1 ratio in currents results.

Hint: I very recently added parameter passing to .models allowing for example, a parameter line spec for each device to be declared as, say, scale=1.5, scale =0.5 with the model declared as:

.model (...Vto={-2.131 * scale} ...)

:-)

?

Jfets are brilliant as front end amps for guitars. You can get ones with <

1nv/rthz input noise. They gave, essentially, zero gate current noise, which for a bipolar loaded by 1H on its input, might well generate huge amounts of noise.

Kevin Aylward

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Reply to
Kevin Aylward

^^^^^^^^^

^^^^^^^^^^

Kevin,

You're contradicting yourself...

Phil also indicated that this JFET has a 2.5:1 spread, and that he uses them around Vgs=0, so that the spread is entirely Idss only -- no effect from Vt except as it relates to Idss.

True, the impact from several transistors being on the "1" end of the range will be small relative to the current drawn by those on the "2.5" end (assuming an even distribution in the reel), but with up to ten in parallel, even that spread gets averaged out. Furthermore, the advantage is still strictly monotonic: going from N to N+1 devices, even if the additional unit has 40% the transconductance of the rest (and therefore about 4% of the total at N=10), the total is still going up, and noise factor, down. So I don't get what the confusion is.

As for distributions: Phil, I don't suppose you've collected any data about typical batch or reel distributions from various manufacturers? Do they tend to match well or not?

Tim

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Reply to
Tim Williams

On a sunny day (Sat, 15 Nov 2014 08:10:57 -0000) it happened "Kevin Aylward" wrote in :

Oops:

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possibly. :-)

I do not remember why I added so many in parallel. I think it worked better:

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Reply to
Jan Panteltje

Am 15.11.2014 um 09:48 schrieb Tim Williams:

I have measured IDss for about 100 BF862 and nearly all were around

12.x mA. A few at 11 and a few upto 15. I wanted one from the upper end of the data sheet range. Nothing. All were from the same tape.

I remember that MPF102s were said to have just in common that they were n-JFETs, that what remains when everything consistent and interesting has been selected out.

regards, Gerhard

Reply to
Gerhard Hoffmann

Bill and Kevin seem to be thinking of FETs biased well below I_DSS, in which case the pinchoff voltage spread will be a problem, but that's not what I'm writing about, a-tall a-tall. A bootstrap is a glorified source follower, and mine usually have other bells and whistles, often including local shunt feedback, a drain bootstrap for the bootstrap FET, and an op amp controlled current sink to servo V_DS to zero volts. (Getting low noise in a photodiode front end is easily valuable enough to pay the freight for these sorts of extras.)

As you say, when you run parallelled JFETs at zero volts G-S, they're all conducting heavily, so they work fine. The production spread in N parallelled devices is no worse than in a single device, and statistically will be somewhat better. (I doubt the spread is really random, so the improvement probably isn't 1/sqrt(N).)

So if the circuit works OK with random FETs from the bin, with N in parallel it'll work N times better on average.

IME most BF862s come in at 15 mA +- 3 mA, but I've probably only seen devices from a few batches. Devices from a single reel seem to be fairly reliably within 20% of each other, to the point where I've used them to temperature compensate each other as one does with BJTs. You do have to allow for the full specified I_DSS spread, of course, or else use selected devices, which is a huge pain with T&R.

Cheers

Phil Hobbs

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Reply to
Phil Hobbs

^^^^^^^^^

^^^^^^^^^^

Reply to
Kevin Aylward

Err.. no. I gave the results of direct paralleling of devices with 0V gate source voltage, when the devices are in normal operating "saturation" region. With manufactures specs of several volts of Vt variation, their can easily be a 10:1 ratio, or more difference in currents. This means that some of the parallel devices are, essentially useless. Period.

Err no... many of the devices might as well just not be there. Its money being thrown away.

For a U309, it specks out as a Vt of 1V to 4V variation. In SS, this gets you 81.3ma and 5.4ma at 0V Vgs and 5V across them. i.e. one might as well not be there.

So, as I said, you have been lucky. This is no way to design for mass production.

Kevin Aylward

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Reply to
Kevin Aylward

Kevin,

You need to go read the BF6862 datasheet, instead of going on about ancient U309s. The BF962's I_DSS range is 10 to 25 mA, but I've never seen one above about 18 mA. Its transconductance range at I_DSS is 35 mS min, 45 mS typical.

When you wire JFETs in parallel, at zero volts G-S, they're all running at I_DSS, and contributing at least 35 mS of transconducance. These are datasheet parameters with guaranteed limits. From a datasheet POV, pinchoff voltage doesn't matter at all.

If I take two BF862s from the same reel and parallel them directly, I get a drain current range that is guaranteed to be between 20 mA and 50 mA, and has a sharply peaked distribution around 25-35 mA. I'm guaranteed to get at least 70 mS of transconductance, which is well outside the range for a single device. Ten devices run between 100 and

250 mA, with transconductance of a minimum 350 mS and typically 450 mS.

All those devices are pulling their weight. There will be some variation in characteristics between amplifiers, but this will be no larger than with a single JFET, and will generally be smaller due to the statistics. One does have to design for the high current edge case, to avoid e.g. saturating the current sink or roasting some resistor, but that's just normal stuff.

If I need

Reply to
Phil Hobbs

In many circuits, like followers for example, or anything with ungrounded sources, none of them are likely to be running at their Idss. Some of them could actually be a bit enhanced. So it's probably prudent to run them at a current that practically guarantees that none of the gates will be forward biased. With BF862's, that's not hard...

12 mA per fet should do it. As you say, BF862's are not like your dad's old jfets. A bit of forward gate bias is usually OK, but some circuits might care.

I recently did a photodiode bootstrap that used two BF862s in AC parallel but DC separately biased. Having resistor packs around, that only added one capacitor overall.

(We run some jfet type gadgets, mostly mesfets and phemts, with forward gate bias. Mesfets ehnance maybe 50% above Idss, phemts can be

2:1 before the gate current gets dangerous.)
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John Larkin         Highland Technology, Inc 
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John Larkin

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