isolated DC/DC converter

The Coiltronics DRQ-series dual-winding inductors have M's of just around 0.99, so I can expect a couple of uH of leakage inductance to soften things up, just about the right amount maybe. And I can always slow down the fets a bit, too.

John

This one runs at 50%. For the DRQ127 inductors John is using he'll need a version with lots of inductance so it won't saturate much at 24V and

100-200kHz. Thiose have very little leakage inductance.

I'd at least put the inductor in, and bridge with zero-ohms it if not desired. Often the noise siuation makes it rather desirable though :-)

--
Regards, Joerg

http://www.analogconsultants.com/

Push-pull, which means 100%.

Just slow down the FETs so they will operate kinda linear at the edges. This will also absorb the inductive turn-off spikes on the drains.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

Can't get to zero transition time. At 100kHz even a mere 500nsec per transition adds up to 10%.

Those aren't necessarily the problem. What I like to keep muffled are the current spikes into the secondary caps after each polarity reversal on the primary side. This stuff tend to magnetically couple into things where one really doesn't want to see it.

--
Regards, Joerg

http://www.analogconsultants.com/

This is of general interest for low level work.

Part of the problem is the huge difference between the supply voltage,

24V, and the LSB with a 20 dB op amp input gain. The lsb with a 2v p-p adc is 2/2^12 = 488uV. With 20dB input buffer gain, the lsb is 48uV. The supply is 24V, so the total attenuation required is greater than 20*log(24/48e-6) = 113.979 dB

That is going to be extremely tough on a pcb when the source and victim are only 2 inches apart.

The issue is to minimize fast transients, either voltage (capacitive charge/discharge) or current (diode snap off, turnon).

I wonder if we are examining all the alternatives. For example, synchronous rectifiers, buck converters, and other methods of dropping the supply voltage to the desired level. For example, here are some descriptions of synchronous rectification with some examples using buck converters:

Synchronous Rectification Tutorial

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Maxim: AN652-1 Synchronous Rectification Aids Low-Voltage Power Supplies

Synchronous Rectification in High?Performance Power Converter Design:

Control Driven Synchronous Rectifiers In Phase Shifted Full Bridge Converters:

The Implication of Synchronous Rectifiers to the Design of Isolated, Single-Ended Forward Converters

Another approach might work if the adc readings are not needed continuously. Then it might be possible to charge a fairly large capacitor during the off time, then turn the power conversion off while the adc is active. A simple linear regulator could be used to keep the supply to the ADC constant during the measurement.

The best approach is to control the noise at the source. If you can eliminate it, the SNR is infinite. No amount of filtering can achieve that.

Mike

The ADC is an LTC2242-12. Its input range is 2 volts p-p, and I catually have 3V p-p coming into the board. I gain it up a little and throw away half in a 70 MHz lowpass filter, so I never have a bunch of gain.

Yup, an LSB is 488 uV at tha ADC. Heck, cell phones have switching regulators and work with microvolt inputs.

See my other post.

John

This looks pretty good:

That little IR driver chip is really very nice. It has a 1 us anti-shoot-through delay, and with 270 ohm gate resistors everything is nice and trapezoidal, sort of what I had in mind with the original circuit idea.

Thanks for the discussion and ideas.

=======================

As soon as we started programming, we found to our surprise that it wasn't as easy to get programs right as we had thought. Debugging had to be discovered. I can remember the exact instant when I realized that a large part of my life from then on was going to be spent in finding mistakes in my own programs.

? Maurice Wilkes discovers debugging, 1949

======================

I'm thinking that I may spend a large part of my life from now on designing power supplies.

John

The three terminal pass regulator showed up as soon as it was physically possible to integrate the pass element. They could have stuck 5 or more pins on it and some bright sparks did just that, and continue to do so with varying success.

Then there's the 431 shunt regultor........

The 3842 came out in a field flooded with more elaborate alternatives. It sparked a flood of pin-compatibles, with moderate improvements or variations.

Designers seem to be afraid to do the same basic thing with the integrated buck converter, or any other simple power conversion function - even simple power drive circuits. Either the market share isn't attractive enough, or there are too few linear start-ups with both the IP, and the need to grab market share.

You may laugh at the 555, but........

I'm not arguing for internal simplicity......just external functionality first, with small signal or 'intelligent' features to follow as optional; let their value be determined by subsequent sales volume.

RL

I generally just use a cmos inverter and buffer it.

RL

So how much crosstalk are you getting under load? That's the real purpose of the thread.

It should show up pretty good in a FFT.

Mike

Different technology. You have 70MHz bandwidth, they are mostly spread spectrum if I'm not mistaken. So their bandwidth is a lot less. Also, you have 24V, they probably have 4.8V or so.

I wonder why they would need a switching regulator. Don't they automatically adjust the transmit power to the minimum necessary to give acceptable signal level at the tower?

Anyway, with no gain at the input, you are looking at

20*log(24/488e-6) = 93.83 dB

That will be a lot easier.

I'm still designing the board schematic, and The Brat will do the board layout starting late this week. It should be interesting, with the 250 Ms/s lvds ADC, the analog front end, a Cyclone FPGA, connectors, and the nine power supplies, all on a fairly small board that goes in an extruded box, namely no air flow. The only way to get serious cooling is through the four mounting holes/spacers out to the box, so all the hottest stuff, like the 2.5v regulator, have to be crowded around those spacers.

The LTC2241-12 ADC is tiny and dissipates 710 mW typ. That's awful. The power and thermal bits are getting to be worse and worse these days.

John

Found the reason for the regulator:

[...]

The reason for this phenomenon is that the power consumption of a mostly digital CMOS circuit is proportional to the square of the supply voltage (ie the battery voltage if the circuit is operated from the battery directly), while if one adds a linear regulator in front of this circuit the power consumption will change only linearly with the battery voltage.

[...]

The role of voltage regulators

The voltage regulators in cellular phones are used to accomplish different goals, aside form their basic task, which is to increase battery life:

1. To step down the voltage between the battery and the different sub-circuits that require lower supply voltage, or to step up the voltage for sub-circuits that need higher voltage than the battery (like SIM card, backlight LED, etc.). Occasionally a buck-boost type regulator is required to generate a voltage that is between the maximum and minimum value of the battery voltage.

1. To isolate the different subsystems from each other. This is important in the RF section, and also between digital and analog/mixed signal circuits. Using LDOs can be cheaper and more area efficient than adding the traditional LC isolation filters that are used in the supply lines of RF circuits.

2. To isolate sensitive circuitry from the transient voltage changes of the battery. This is especially relevant in GSM phones where the PA operates in a 217 Hz pulsed mode with 12.5% duty cycle. The high current of the PA, typically up to 1.6A, can cause a voltage transient of up to 0.5V due to the combined effect of the battery's ESR and protection circuitry. The PSSR of the voltage regulator significantly reduces the supply transient seen by the phone circuits.

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"

Mike

( where 'it' refers to a good idea)

Oh, if you don't steal it, I will. Ars magna, vita brevis, after all. More to the point, nobody steals my best ideas: I have to ram them through under fierce backpressure.

I attribute it to my being a bad explainer, actually... 'cuz I'll leave out the obvious parts, and no one agrees which those are.

FPGA and uP and custom logic has ever-decreasing core voltages. 0.9 volts is common nowadays, and battery voltages are much higher, so a switching regulator is needed to conserve battery energy.

John

They mention this in Item 1, as well as a requirement for higher voltages for the display. So they probably have numerous regulators on board.

The article goes into some detail on the cost vs benefit of switching vs linear regulators. They conclude a switcher costs a lot more, and doesn't give that much improvement in talk or listen time. But those are 2002 numbers, so things have probably changed a great deal since then.

But they also add a configuration for a LDO that is insensitive to the output cap. This might be interesting for some, so here's the url again:

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Mike

Mere 500ns ? The things have improved somewhat since 2N176 or TIP35. I run DirectFETs with about 5ns of dead time.

This is a big problem of SMPS. An inductive kick of high current on turn-off is difficult to divert, especially if there is considerable amount of energy.

Quasi-linear operation during slow turn-on takes helps with that, too.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

I found an interesting effect: I'm using the IR half-bridge driver and a pair of n-fets, capacitively coupled into the transformer primary. The driver has a full microsecond of anti-shoot-through dead time, and I'm running at 150 KHz. I was playing with snubbers and it gets interesting with about 2 nf of capacitance, but no resistor, to ground. When the fets turn off, the magnetizing current (plus some current from leakage inductance, probably) dumps into the cap and makes a nice linear ramp from rail to rail, just in time for the "new" fet to turn on and pick up the load. So the overall waveform is a very pretty trapezoid, but no power is lost to the slowdown. It's a slightly-resonant converter.

I can get just about the same waveform with biggish gate resistors, so I'll lay out the board with the option of using the cap-only snubber, and play with it if I have time. It did seem to improve efficiency a little.

John

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

Power supplies have it easy, induction heaters have to do it for any combination of load inductance and output frequency.

This picture's about two years old, about halfway through my basement ramblings:

Nowadays I'm doing the same thing, at almost half a MHz, and a couple orders of magnitude more power. Not that SPICE is necessarily very representative of things like switching loss, but cranking down the timestep seems to give reasonable numbers -- even at maximum frequency, I've got switching losses lower than conduction. The new boards come in next week, I can't wait to blast some amps through them.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms