Is this right? 1125MHz 14-bit dual channel acquisition

Back in time when 8 Bit/20 MSPS was bleeding egde we used one of these for ultrasonic reactor wall testing. We got an additional ADC from TRW in a plexiglas cube. One could see the reference ladder and the comparator string with the bare eye.

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It is the large black chip on the blurred board on the bottom right. The white blob reads "TRW". The rest of the boards is a real-time averager.

Some years later I condensed the entire board set to one board with some Xilinx FPGAs. It had a pipeline 20 stages deep.

There was an interim solution with Fairchild F100K, but that ran too hot.

Cheers, Gerhard

People used to make true-flash ADCs, at 6 bits or so. There was a "half-flash" ADC with 8 or 10, I think; each comparator generated two bits.

The problem was power. The nice thing was low pipeline delay.

One of my many former employers made a Camac module 6-bit 50 MHz ADC out of discrete comparators. The model number was, appropriately, SAD-650.

You gotta really want to do something like that. ;)

Cheers

Phil Hobbs

torsdag den 4. november 2021 kl. 16.40.12 UTC+1 skrev snipped-for-privacy@highlandsniptechnology.com:

I wonder how well a string of resistors and 32 LVDS inputs on an FPGA would work, though it is a lot of pins

On a sunny day (Thu, 4 Nov 2021 11:39:05 -0700 (PDT)) it happened Lasse Langwadt Christensen snipped-for-privacy@fonz.dk wrote in snipped-for-privacy@googlegroups.com:

In reverse on that board I showed there is an R2R DAC on 8 FPGA output pins for video out. Worked!

There could be cases where just a few bits would do.

One could use external dual LVDS receivers as the comparators. They are cheap and fast and pretty good.

Again, no pipeline delay.

Long ago, I used to use a nice TRW 8-bit true flash (1038B6C, 20 MS/s) that was even second-sourced. It came in a 28-pin wide CERDIP.

The other main issue with flash converters (besides the horrible resolution vs. power and die size issue) was sloppy aperture time, on account of the capacitive coupling from the signal to the (high-Z) resistor string at the comparator inputs.

Cheers

Phil Hobbs

torsdag den 4. november 2021 kl. 20.08.49 UTC+1 skrev Jan Panteltje:

sure, DAC is a lot easier

and then there's his kind of "hifi" nonsense

We have used the LVDS inputs of an FPGA as real comparators, but ground bounce noise and crosstalk keeps that from working at the millivolt level.

The high-end audio people are lunatics. Golden ears get expensive.

On a sunny day (Thu, 4 Nov 2021 12:44:00 -0700 (PDT)) it happened Lasse Langwadt Christensen snipped-for-privacy@fonz.dk wrote in snipped-for-privacy@googlegroups.com:

Yes 24 bit audio at 384 kHz is the minumum you need for true fidelity !

On a sunny day (Thu, 04 Nov 2021 12:31:20 -0700) it happened snipped-for-privacy@highlandsniptechnology.com wrote in snipped-for-privacy@4ax.com:

Or have the R2R DAC drive a comparator and do successive approximation. With high speed FPGA and not so many steps needed it could be fast. I did something like that long ago, I like successive approximation.

With CMOS gate drivers and 0.05% resistors!

We do delta-sigma DACs in an FPGA. Add a feedback loop! Join the slowest-possible-ADC competition.

There's also a hybrid DAC, a few bits of ladder, but d-s dithered to higher resolution. Worst of both worlds.

One could do a cheap single-slope ADC with an LVDS input. The entire ADC would become one R and one C. Shared across multiple channels.

torsdag den 4. november 2021 kl. 21.42.06 UTC+1 skrev snipped-for-privacy@highlandsniptechnology.com:

you can also do d-s down to a few bits and the do those bits with PWM reducing the switching rate

or

or you could do a real d-s, needs an integrator but it keeps the comparator threshold at VCC/2

On a sunny day (Thu, 04 Nov 2021 13:41:58 -0700) it happened snipped-for-privacy@highlandsniptechnology.com wrote in snipped-for-privacy@4ax.com:

When doing the successive approximation it is a good idea to have a sample and hold circuit, so 1 extra output pin from the FPGA, to keep the voltage constant when checking,