Is microprocessor an integrated circuit???

Intel 4004, 8008 Motorola 6800, 6801, 6805, 6809

Now take back what you said. You can check your favorite source, Wikipedia if you don't believe me.

The 6502 was reverse engineered from 6800. Both were not microcoded. Motorola's first microcoded CPU was the 6800, the 6809 was the last uP design from Motorola that wasn't microcoded (late 70s). You will see that around this time was when uP designs changed from hard wired to microcode.

While the 68000 through 68040 are microcoded, you are right, the 68060 and it's descendants are hard wired. MC68300 is a descendant of the 68020 and therefore microcoded. While the core CPU is hard wired on the ColdFire, it has an on chip TPU (time processing unit) that is microcoded,

I meant to write the first microcoded CPU from Motorola was the 68000, three zeros.

Actually, the TPU is a microengine that executes something that looks like microcode, but it's a one-level structure, so I wouldn't call it a microcoded processor either. I wouldn't actually call the TPU a computer at all, just a state machine.

John

Because he's a pain slut, a person who need continuous public humiliation. Usenet seems to attract this type.

John

You've been shown excerpts from the 'C' spec. Why don't you hang it up and admit you're wrong?

IBM isn't mainstream? The 'C' specification isn't mainstream? What do you want an engraved invitation? Yeesh!

^^^^^^

The word *you're* looking for is "inept".

If your smallest addressable unit, larger than a bit, is a million bits, then you have a million bit byte. What's so hard to understand?

Go for it. Sell the idea to some VC types and see if anyone bytes!

coward

Your link didnt work, wise guy. Besides, thats copyrighted material.

If you know the spec so well, why not show how the mainstream industry in

The use of a byte with a parity bit? It doesnt count inside the byte area and therefore doesnt make a byte 9 bits. I know this is a rather advanced conept.

How about we redefine the byte to be 1 million bits? Then to the slower types we can use a metric system equivalent so anyone can follow along.

the decibyte, microbyte, centibyte

This is a very contentious subject, severely lacking in an apparent interest in facts, only bar room style babble, like drunk talk. People jumping in dont even care what it is, micro program counter? whats that?

Unless you can show with evidence in reality? Why should I consider the sarcasm of someone like (Craig) who seems more interested in males having a male sex organ in their mouth? Perhaps it would help to seek details on processor internals on technical sites, rather than sites showing males having relations with other males. Otherwise try harder to distinguish between technical concepts and the male to male sex hangup thing

Plonk!

I've done the same. Bradley is either a incredibly thickheaded moron incapable of understanding even the most simple of arguments or truly a troll, probably the latter. Both get the killfile.

On the 68332, you can tell the TPU to run out of the 2 kbyte CPU internal ram (instead of the standard masked rom set) mainly for debugging TPU microcode in preparation for making a mask. But I guess you could just run that way. The TPU is really a timing state machine, not at all a general-purpose CPU. There are two main standard mask sets, both heavily weighted towards engine control sorts of operations. It's a very neat thing, but a real pain to program.

John

snip

Is a TPU really microcoded?, isn't it just a CPU running out of ROM, you can get other motorola CPUs with a TPU that can run out of RAM so you can program it yourself...

-Lasse

In the 68k architecture there is no IO, all IO is performed with memory mapped peripherals. The TPU is one of these peripheral devices that just happens to be on chip.

Not all ColdFire parts are 2k. I'm not sure how many different sizes are available, but the MC68336 has 3.5k TPURAM module.

When you put the TPU it in emulation mode, the memory gets unmapped from the CPU address space.

My point is that while the CPU is hard-wired, the peripheral processor is microcoded. Neither fact diminishes it as a microprocessor.

The part I quoted was the only thing he wrote I agree with. No sense in buying a drunk another round.

I'd forgotten SID and SOD, but I guess...

I don't see a string compare as being a real issue with RISC. PowerPC has string moves between memory and registers. I suppose you could argue... The 8086 MOVS is another kettle though.

ADD ,R is another example of a no-no in a RISC ISA.

Good grief, you're using IBN (Intel Backwards Notation),

Opcode destination, source

John

Two memory accesses (read-modify-write).

The idea is to be register-rich so the instructions can be simple. THe original philosophy was to have instructions "execute" in a single instruction. Put two memory references in there and things get ugly.

Next up on the agenda!