So what are the main dissipation mechanism in class D stage ? I can think of two important mechanisms:
With slow transistors the power dissipated during turn-on and turn-off transitions can be significant. With constant sample rate PWM, the number of transitions per second is constant regardless of audio volume.
The transistor ON state Vce(sat) causes some power dissipation. At full power, the transistor duty cycle is nearly 50 %, so there is a single Vce(sat) all the time either in the top or bottom transistor. However, at low audio volumes the transistor duty cycle is very low and most of the time, neither transistor conducts and hence the average Vce(sat) losses are very low.
Any other significant loss mechanisms ?
It appears that the absolute dissipation is worst during full power, dropping at lower levels, hence if the heatsink is adequate for full power, it should also be sufficient for low audio levels.