I hate substrate diodes!

If you want to digitize a "bipolar" signal, you swing the highside signal pin from 0 to +4.096, and you have to hold the lowside signal pin at 2.048+-0.1. If the lowside pin isn't right on 2.048, the ADC has a horrible temperature coefficient. OK, you can argue that the datasheet suggests this in one place. But I wonder why they did it this way, and why they didn't explain it in the clear.

So it's "differential" and it's "bipolar", but not at the same time.

Again, when parts have gotchas, they should be described clearly, not hidden like easter eggs. I spent a lot of time on the phone until I found someone who knew about this. He said they nabbed the ADC core from some other project, mumble mumble.

They also didn't note that a little current into one 130-mA rated esd diode messes up the entire ADC. We're all supposed to know this, I guess.

John

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Is this foundry? Getting the truth from a foundry on the details of their process depends on your relationship. Like I've mentioned before, I've found processing steps in a process where I actually worked that were kept secret. There are a few analysis companies in the valley that probably know the reality of a process better than the in-house published specs.

Not to get my arse sued, but I bet if you take any published process spec for the sheet rho of the substrate, and then pay a firm to measure it, the numbers will not match. These semi analysis firms are simply amazing. You feed them parts and money, they can show you the devices from the "side". Instead of sheet resistance, they can give you a profile. I never worked on cutting edge digital processes, but I bet you AMD pays to get Intel wafer analysis and vice verse.

No, it was the Microelectronics Research Lab at IBM Yorktown--they had a small but complete 8-inch fab line, including an ion implanter, epi reactor, atomic-layer deposition, high-K gate insulation, dual damascene copper metal, low-K, chem-mech polish, wafer bonding and thinning, 193 nm litho, three Leica e-beam writers, focused ion beam/TEM characterization, MEMS processing, yada yada yada. Amazing place, really--many of those techniques were developed there originally. I ran a few of the tools myself, and had colleagues to help with some of the rest. I got on well with about 95% of the fab engineers, though there were a couple that really didn't want to be doing anything but CMOS, and a couple more that only wanted to work on high priority projects for career reasons.

By the time I was done, I was writing all my own run sheets and tweaking my own parameters, but I only had one or two run slots and the full process was ~200 steps, so it took a long time to get data even when it all worked. I sure learned a lot about various tricks that didn't work for weird reasons. Of course I also learned a lot of things that worked great, just not as many. ;)

Cheers

Phil Hobbs