I hate substrate diodes!

Didn't Ravenhorde (sp) just have the same problem? Is an opamp/ comparator driving some fet too big?

George H.

Obviously I don't have the layout in front of me, but basically they put in collectors to gather the current flow when you forward bias the protection diode. But you can't collect all the carriers. They spew out into the substrate. I suspect the 130ma limit mentioned is just so the part doesn't latch up. It is a decent spec for a linear part on what I guess is epi cmos.

The only way to get around this problem on a single supply part is to use parts built on insulator. In the day, it was silicon on sapphire. Now they call it silicon on insulator. (silicon dioxide). There are a few companies with such a process. For analog, Elantec comes to mind. You could check the Intersil catalog to see if they still have product on insulator. It won't be cheap.

Have you looked at dual supply parts? Then all you have to worry about is pulling the input beneath the bottom rail.

This is why general-purpose instrumentation is so expensive and to some extent independent of the price of the semiconductors that we think would do the job. As a producer of general purpose instrumentation that probably doesn't help you :-(

I mean, everytime I price out deep-buffer digital storage scopes I think to myself "I could buy an ADC and a FPGA and some DRAM and do this for one fiftieth of the cost".

But way less often do I have to take the covers off my old Tek 465 and actually appreciate all the stuff the scope does for me. Not to mention the build quality - jeeze, so many electromechanical switches and the thing is still extremely reliable after a couple of decades.

Oh, BTW, driving one channel of the 465 way off scale does mess up the other channel at least a little and there's no ADC to blame. And I find myself still using the 465 way more than any of the digital scopes I have.

Tim.

SOS is a 1970s technology--really gold plated, Si epi grown directly on oriented sapphire. It was developed by RCA, I think, but I remember HP using it in some early computer of theirs because of the good thermal properties. It's still used in some rad-hard chips because the insulator doesn't get leaky with radiation.

Modern SOI wafers are made by one of two processes: wafer bonding, i.e. bonding two wafers with blanket oxide together and then grinding and polishing the top wafer to the desired thickness, or SIMOX, i.e. very heavy oxygen ion implanting, followed by annealing to make the oxide precipitates into a very thin but continuous oxide layer. (There are cute methods for wafer bonding, e.g. using hydrogen implanting and rapid thermal anneal to make the top wafer delaminate, leaving a thin Si layer that can be chem-mech polished easily. Magic.)

It's really only the wafer cost that's different between SOI and bulk, no? At IBM, I used custom bonded SOI wafers that were pretty expensive--about $10k per box. They were 0.3 um Si on 2 um bottom oxide (BOX). The logic guys were all using standard bonded or SIMOX wafers that were much much cheaper.

Maybe it's a foundry issue.

Cheers

Phil Hobbs

Most good ADCs are single-supply, pseudo-bipolar things lately.

This is about what we're doing.

ftp://jjlarkin.lmi.net/ADC_frontend.JPG

It will be a 64-channel, differential-input, programmable gain ADC board. My job on this one is to spot hazards, and I've found five or six so far.

One overloaded input can spray charge around inside a DG408

Mux outputs can carry charge between channels, crosstalk

The overload recovery of the IA isn't specified, so we had to figure it out. Adds about a microsecond to the scan, which we can work around

ADC substrate diode problem, as noted

ADC Vcm requirement, as noted

and a few others.

IC manufacturers seem to deliberately hide gotchas in their data sheets, when they should emphasize them in boldface, red text in garish boxes. Even their datasheet examples often have hazards. They make their own parts fail, and make their various customers spin boards over and over. I don't understand the logic there.

Hittite really nailed me on one RF switch. The datasheet says in huge type "DC-4 GHz." But it actually doesn't work right below about 100 MHz. I complained, and they said that I should have studied the S11 data in the S-param files (not part of the datasheet) and figured that out myself. Turns out there are caps in series with their termination resistors, but only the resistor is shown on the datasheet simplified schematic. I asked them the value of the cap, and they said "that's proprietary."

John

here is a trick that can reduce __some__ of the crosstalk between channels in the mux...

pick one of the 8 input channels of the mux and tie it to ground. (yes you have to give up one channel)

program the software so that you don't switch from one input channel to the next directly, instead you always select the grounded channel between active measurments. (yes you have to give up some speed)

this dumps some of the charge ..

Mark

It really made the layout and logic ugly to use seven channels per chunk, so we added 2/4 of a DG441 per mux block, to discharge the mux output nodes. We'll switch the mux address but disable the mux, switch the PGA gain, and turn on the discharge gadgets, wait about a microsecond, then enable the real signal path. The PGA can take about a microsecond to recover from being railed, so the discharge overlaps that and centers the PGA in its slew range. Each mux hits a new channel every 8 microseconds. The ADC digitizes at 500 KHz, and scans four PGA outputs. The choreography is complex, but I don't have to do it!

This stuff is fun.

John

There is also the V-Groove Dielectric Isolation process.

Burr Brown (now part of T.I.) used this on many of their high performance analog parts. Check with them & see if they have an ADC built on this process. Art

Hmm. I didn't think any of the major players make their own wafers anymore.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

Burr Brown _did_ have their own processing. I don't know since the TI acquisition.

I thought Fairchild did also. But I just checked the files from my last project with them... TSMC. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

But to do this, they'd need to _make_ their own wafers, not just process them.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

Aha! Missed your point. Wafer manufacture is an entirely separate business from "processing". ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

BB purchased the raw wafers, and etched the V grooves in house. I don't recall which of the oxide growth, poly growth, and lapping steps were done out of house, but at least one was. All subsequent processing was done in house. I have no idea what TI is doing with the process as everything has moved to Dallas and the Tucson facility is shuttered. Art

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I don't think anyone is on bulk anymore, just epi. It is all a matter of cost. OK, I just proved myself wrong about bulk CMOS use:

Ion implanting isn't all that simple nor cheap. One place I worked would send the wafers out for implant. This I found out when somebody screwed up and failed to do one of the implants. Doh!

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But I think TI did makes their own wafers and even masks. Things are dynamic, so this may not be true today.

"Ooooopppss, sorry about that." Kind of hard to do the implants after metallization.

Processing is a very poorly understood field, even today. If you take a process that's running 90% yield on one thing, and try do do something that's 15% different, e.g. thicker films or a longer etch, you can get all sorts of surprises.

I've never done any normal processing--just silicon photonics stuff--but I got a whole lot of bad advice along with the good advice, even from experts. Some major fraction of all the significant advances in silicon technology came out of the IBM Watson Lab, so most of these folks were very good indeed.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

What you mean to say is there are good single supply ADCs. Good is another story, especially if you have this signal conditioning problem. A dual supply chip will not have such issues. Or more correctly states, a dual supply part could be designed not to have such issues.

There is the datasheet, and then there is electrical behavior. I have had a part or two in the past need a rev because it met the electricals (i.e. datasheet), but applications didn't like the behavior. What I learned to do is ask application what they plan on doing for a bench test, then look at the design for problems.

Clearly AD apps never tried abusing one input to see if it effects the operation of the rest of the chip. Now I don't think the datasheet requires this, so AD is fine electrically, but the customer is mighty damn pissed about the behavior of the part.

My attitude is if pin of a chip touches the outside world, it needs the utmost scrutiny.

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Two schools of thought on processing. If the product is high volume, they will tweak the process a bit to get the best yield. RAM comes to mind. Otherwise you live with the limits of the process. So many companies are fabless these days that they have to live with what they got.

While I never worked for Intel, I got to run product through one of their fabs just like an insider. [A long story.] Intel would run "factorials" on high volume products.They would tweak bits of the process to see how it effected yield. This produced two kinds of knowledge. First, you knew what element of processing would improve yield if you wanted to tweak the process for the product. Second, you knew what would kill the yield. There are times in processing a wafer lot where you know a step was not done properly, but perhaps it was just off a bit. Rather than scrap the lot, you might finish it if you believe the error won't kill the yield. This is really an ugly QA issue since if the process was off a bit, QA might insist on a burn in test.

It's probably been 3 decades since any board stuff did incoming inspection, yet they believe all their incoming parts are just like they arrived at day one. This is hardly the case.

That makes sense. Tweaking a running process is mostly a design-of-experiments problem, where you figure out what tests to run to get the most useful data at least cost. You already know the process works, which is a huge help--it's troubleshooting rather than design/debug.

Designing a process for building something new, e.g. the next node on the CMOS roadmap, is much more fraught. And when you're a non-processing guy trying to do something altogether new, e.g. integrate antenna coupled tunnel junctions on planarized SOI optical waveguides, life gets really exciting. I spent a lot of time down rabbit holes because I trusted expert advice earnestly given, but maybe less than if I'd tried doing it completely on my own. Those were smart folks who were doing their best to help, too.

Processing is hard.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net