How protection diodes 'wear out'.

All, I saw this and thought of all those FPGAs out there on high speed busses. Quote:- "If you depend on ESD-protection diodes to clamp transients on a high-speed bus, you risk burning them out. Because a burned-out diode fails in the open state, obliterating its clamping effect, the next ESD blast that roars through your system will likely cause permanent damage."

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I wonder if the FPGA vendors have any figures to plug into the equation given in the above article? That way, those engineers who ignore SI issues could predict when their designs will fail and prepare to get another job! Paul? Austin?

Cheers, Syms.

Reply to
Symon
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The referenced article does not mention diode burn-out, but rather the failure of metal traces leading to the diode. Rest assured that Xilinx outputs and their metal traces can conduct and withstand (ad infinitum!) currents up to at least 12 mA, probably considerably higher. Now, if you intend to zap the pin with repeated capacitive discharges of 10,000 V backed by several 100 pF, that may be a different story. But I have not seen anything like that in real life. ESD damage occurs usually on the bare device, before it is soldered to a pc board.

Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

Symon,

We design for extreme electromigration, as we have no clue what our customers will do to (with) our parts.

They are designed for in excess of 60 mA. Now that doesn't mean you can go and use the clamp at that level, but we do not see any EM failures in ten years of accelerated tested.

On the other hand, ASIC IO cells (and 'hardened' logic versions) are as small (cheap), and fast as possible, and I have been told that they can (easily) be blown out by abuse.

Aust> The referenced article does not mention diode burn-out, but rather the

Reply to
Austin Lesea

Yes.

The point I think the author was trying to make was that if someone used the diodes (and by definition the metal connections) to clamp a badly terminated high speed bus, the repeated clamp current, albeit brief but in excess of (say) 12mA, could cause a failure in time. Even though the average clamp current was far below the 12mA you mention.

Indeed, as I said, ESD is something different, and well understood. I was just curious about designs where the diodes are relied on to repeatedly clamp over/under shoots. The article implies that the diode/metal connections are there *only* to protect against a few ESD zaps in a lifetime, not repeated stress caused by bad bus design. Which is something I didn't know!

Cheers, Syms.

Reply to
Symon

I bet you see a few horror stories!

OK, sounds as though it's not a big deal for Xilinx parts then. Thanks for the reply, Syms.

Reply to
Symon

Diode failure mode is typically short circuit, unless energy follow-through is sufficient to blow bonding wires or bonding pads open circuit. The latter is seldom the case in impedance-limited circuits.

RL

Reply to
legg

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