OpAmp input protection against ringing

IMHO you'll be OK. If you're the suspicious sort you may want to breadboard the op-amp stage and measure the supply current with a wimpy source trying to pull the thing above or below the rails -- if the current doesn't jump, proceed.

--
www.wescottdesign.com

Should be OK. Most opamps have well-behaved ESD diodes. Triggering an SCR latchup is improbable at 100 uA. But, as Tim suggests, you might breadboard it, observe the clamp behavior, and push in some more current just for fun.

Some opamps go temporarily insane if you drive them a little past the rails, and turn those diodes on. LM324 is the classic example.

This amp is protected to hundreds of volts overload; depletion fet current limiters into the opamp ESD diodes.

--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

very interesting question. Those ESD input protection devices are 'specced' to take on a certain amount of a joule hit, translates to the amount of energy, and local heating, that little area can do. Working backward from that spec and determining how much absue your input can heap on the input line, you should be able to get some time of numbers to justify doing, or not.

My old rule of thumb was 'how much reverse bias current can you put through the b-e junction on a small transistor' [also a small area] From memory somthing like 50mW ?? then applying some margin make that

10-20mW ok now you said 5 excess volts at 100uA, that would be 0.5mW seems reasonable. But depends on how robust the IC designer made that particular ESD device. So check the 'protection' spec to get an idea.

Jim Thompson, or Alex, or Aylward could probably tell you more precisely.

If you've equipped it to handle the rigors of connectors, EMC and ESD, it will certainly stomach any tiny wiggles that go near it.

Tim

-- Seven Transistor Labs Electrical Engineering Consultation Website:

The equation is different when power is on, and when the exposure is continuous. Some chips go nuts when the inputs are out of bounds, some don't. Some just give you the wrong answer, some let out the magic smoke.

Mostly, I think he's safe. I'd probably design in such a chip without even doing the test I suggested -- but if I thought the situation was likely I'd be sure to induce it in testing, and I wouldn't be too surprised if Something Bad happened.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com

Generally you design for a DC current injection, not joules of energy, at least when latch up is involved.

The ESD diode is often the emitter of a parasitic transistor. [Depends on the process.] So you are injecting substrate current, but 100uA is not a big deal.

At this point, it doesn't hurt to give the old lecture about yanking on ESD diodes. When you yank on these diodes, they in turn yank on the power supply or ground, depending where they are connected. Now yanking up on a power supply means that you are now powering the rest of the PCB components through your injector. If the rest of the boards draws sufficient power, then no big deal. But if you yank hard enough, you will lift the entire supply rail of the PCB, which could stress components.

When you bench test a chip for latch up, a dummy load is put across the bench supply so that it always has to source current. Power supplies will only stay within spec if they are sourcing current. If you try to sink power into them, the rail just lifts.

A long time ago, when the world was transitioning from 5V to 3.3V, we had an FPGA with a ton of 5V tolerant inputs, talking to a ton of 5V-powered devices. I wasn't the board designer, but I can't claim I wouldn't have done anything differently from what he did.

We had exactly that happen: the 3.3V rail got lifted enough to cause incorrect circuit operation; it puzzled the hell out of several of us, then we all felt quite sheepish when the light came on.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com

I e B

The xilinx schematic for doing 5V tolerant JTAG using series resistors and the ESD diodes have a resistor on power supply so the minimum load is alway s more than what could be injected

-Lasse

Must have, indeed, been a long time ago... today's "5V tolerant" devices don't have an ESD diode to VDD, they utilize the "snap diode" (to ground) approach for positive going ESD pulses. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
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I love to cook with wine.     Sometimes I even put it in the food.

Den torsdag den 20. november 2014 20.03.32 UTC+1 skrev Jim Thompson:

I e l

he

s t n g

CB

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A long time ago there was FPGAs that had real 5V tolerance inputs without the diode to Vdd, it was needed for 5V PCI

but for a long time they haven't really been 5V tolerant but they specifica lly allow higher input voltages as long as they have series resistance so t he current though the diode to Vdd is limited to < 20mA

-Lasse

[snip]

Truly 5V tolerant inputs DON'T have an ESD diode to VDD... PERIOD.

You're not up-to-date on the current technology.

Your statement is only true for those devices that allow you to force current thru the ESD diodes.

On truly 5V tolerant inputs, the input stage literally is allowed to harmlessly float above VDD.

I'm not at liberty to show you how this is done >:-}

Such schemes are also used at outputs of devices to keep them from loading a bus when they are unpowered. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Den torsdag den 20. november 2014 21.42.31 UTC+1 skrev Jim Thompson:

how do you figure that?

Tim was talking about FPGAs and in the part you snipped I said that they used to be truly 5V tolerant with no diode to Vdd, but for a long time they haven't been, they just allow you to make an input tolerate 5V because forcing a limited current into the ESD diode is allowed

-Lasse

My apologies, I missed the specific part number thing... thought you were talking in general about 5V tolerant parts. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

N-fet. Gate tied to source through a resistor. Drain goes to I/O pin. Negative excursion sees a diode. Positive excursion is ESD protected through snapback.

Generally to avoid powered off devices from becoming a load, you employ body snatchers.

These schemes are decades old. You see something similar to the power off technique in LDO designs that can handle reverse power application.

the

had

Seeing others rat themselves out always makes it easier for me to do the same. Thanks.

?-)