Hysteresis without Feedback

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I'm not making much sense of the circuit, which is partly covered by the ou tput graph. What sort of circuit is it?

Hysteresis without feedback:

. + . | . R . |>| _|----o out . ----|

Doesn't work for the DC sweep shown. :^)

Tim

Close ;-) ...Jim Thompson

Well, don't show us how it works.

Anything with hysteresis must store an internal state.

Once embellished, it will be shown. First passes always have bugs.

But doesn't require feedback to store that state. ...Jim Thompson

t the

output graph. What sort of circuit is it?

I'm doing something wrong here, but not seeing what...

Version 4 SHEET 1 880 680 WIRE -704 -48 -784 -48 WIRE -48 -48 -704 -48 WIRE -784 -32 -784 -48 WIRE -704 -16 -704 -48 WIRE -784 64 -784 48 WIRE -704 64 -704 48 WIRE -48 128 -48 -48 WIRE -48 288 -48 208 WIRE -448 368 -560 368 WIRE -192 368 -256 368 WIRE -96 368 -192 368 WIRE -192 400 -192 368 WIRE -448 432 -448 368 WIRE -256 432 -256 368 WIRE -192 496 -192 464 WIRE -48 496 -48 384 WIRE -48 496 -192 496 WIRE -560 528 -560 448 WIRE -48 528 -48 496 FLAG -784 64 0 FLAG -48 528 0 FLAG -704 64 0 FLAG -560 528 0 SYMBOL voltage -784 -48 R0 WINDOW 123 0 0 Left 2 WINDOW 39 24 124 Left 2 SYMATTR SpiceLine Rser=0 SYMATTR InstName V1 SYMATTR Value 10 SYMBOL cap -720 -16 R0 SYMATTR InstName C1

SYMBOL nmos -96 288 R0 SYMATTR InstName M1 SYMBOL res -64 112 R0 SYMATTR InstName R1 SYMATTR Value 100 SYMBOL cap -208 400 R0 SYMATTR InstName C2 SYMATTR Value 0.1 SYMBOL diode -320 384 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMBOL diode -384 384 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D2 SYMBOL diode -448 384 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D3 SYMBOL diode -256 416 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D4 SYMBOL diode -320 416 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D5 SYMBOL diode -384 416 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D6 SYMBOL voltage -560 352 M0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PULSE(-10 15 0 .1 .1 0 0 1) TEXT -608 -88 Left 2 !.tran 0 0.2 0 10u startup

NT

The trick, as always, is in using TANH ;-) ...Jim Thompson

Plus LTspice's idealized elements will cook your goose, because they're idealized around the needs of SMPS's. ...Jim Thompson

thout the

the output graph. What sort of circuit is it?

I don't have any TANHs in stock at the moment :) None in the junkbox either .

The effect I'm playing with is very simple, spice models the diode V drop n ear enough for the purpose. But the output stays at +10v, and I'm not seein g why. Even when Vg ranges over -10 to +12v.

NT

Whatever NMOS model you picked only sucks 1.5mA at full drive. ...Jim Thompson

Many problems. You don't need C1 - it is in parallel with a zero ohm source voltage. C2 is 0.1 Farad. That's way too large, and there is no readon to add it in parallel with the gate capacitance. Delete it.

The biggest problem is the MOSFET. Since you did not select a real device, it defaults to a very small device that cannot carry much current. So you won't see much output change across a 100 ohm load.

Next, you should never use the default semiconductors unless there is a reason to do so. Change D1-D6 to valid diodes.

You should always label every node in the circuit. If you do not, Ltspice will renum,er the nodes every time you make a change. If you were trying to plot N00X, the waveform will show some other part of the circuit.

Finally, to see the effect of gate capacitance, increase the signal frequency drastically.

Try this version:

Version 4 SHEET 1 880 680 WIRE -48 96 -272 96 WIRE -272 112 -272 96 WIRE -48 128 -48 96 WIRE -272 208 -272 192 WIRE -48 240 -48 208 WIRE -48 288 -48 240 WIRE -512 368 -560 368 WIRE -448 368 -512 368 WIRE -144 368 -256 368 WIRE -96 368 -144 368 WIRE -560 400 -560 368 WIRE -448 432 -448 368 WIRE -256 432 -256 368 WIRE -560 528 -560 480 WIRE -48 528 -48 384 FLAG -272 208 0 FLAG -48 528 0 FLAG -560 528 0 FLAG -48 240 M1D FLAG -144 368 M1G FLAG -512 368 Vgate SYMBOL voltage -272 96 R0 WINDOW 123 0 0 Left 2 WINDOW 39 37 59 Left 2 SYMATTR SpiceLine Rser=0 SYMATTR InstName V1 SYMATTR Value 10 SYMBOL nmos -96 288 R0 SYMATTR InstName M1 SYMATTR Value IRF530 SYMBOL res -64 112 R0 SYMATTR InstName R1 SYMATTR Value 100 SYMBOL schottky -320 384 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value 1N4007 SYMATTR Description Diode SYMATTR Type diode SYMBOL diode -384 384 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D2 SYMATTR Value 1N4007 SYMBOL diode -448 384 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D3 SYMATTR Value 1N4007 SYMBOL diode -256 416 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D4 SYMATTR Value 1N4007 SYMBOL diode -320 416 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D5 SYMATTR Value 1N4007 SYMBOL diode -384 416 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D6 SYMATTR Value 1N4007 SYMBOL voltage -560 384 M0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PULSE(0 10 0 2u 2u 0 0) TEXT -568 32 Left 2 !.tran 0 220u 200u TEXT -568 8 Left 2 ;'MOSFET Gate Driver TEXT -344 32 Left 2 !.ic V(M1G) = 0

without the

by the output graph. What sort of circuit is it?

her.

p near enough for the purpose. But the output stays at +10v, and I'm not se eing why. Even when Vg ranges over -10 to +12v.

Bingo, thank you. Changed R to 10k and it works.

Spice plots Vin & Vout vs t, I don't know how to plot Vin vs Vout though.

NT

In PSpice you just click change x-axis variable and select what you want from the list, or type it in if you already know.

I think there's an equivalent in LTspice (I don't create schematics in LTspice, just do a Run, Filename, to verify results are the same in LTspice as in PSpice). ...Jim Thompson

IOW you don't own any transistors. ;)

A BJT diff pair with its output taken differentially has a tanh characteristic. It's surprisingly accurate if you use monolithically-matched devices.

Cheers

Phil Hobbs

I could see something analogous to an over-centre latch, e.g. a diff pair with a lambda diode collector load. That just has local feedback. ;)

Cheers

Phil Hobbs

Initial conditions can be problematic.

Ha, yes. I just didn't bother to delete it, makes no difference.

Sure. I put it there in case the fet model has leakage added.

Their Vf is a fixed 1v drop. For this proof of concept it doesn't matter.

or remove the capacitor, as it works using gate capacitance already. Again it was just a quick proof of concept, since it ran in around a second I didn't worry about the time scale.

NT

t the

Just think about how an iron core implements hysteresis and copy that. That 's what mine does. Jim's has way more gain. I'm not familiar with his diagr ams though.

NT

Any latch has an internal state: the stored base charge in a saturated transistor, for instance. Thermal noise would reset the latch otherwise.