How to choose high speed transistors for FET gate driver?

Sep 22, 2009 5 Replies

Hi - I'm trying to make a discrete gate driver for the synchronous N- MOSFET in a boost converter. The output of the boost converter is 43V max, and I'll have another 10V or so sitting on top of that for the N- FET drive. That is being generated by the classic diode/capacitor bootstrap supply - so it's pretty weak and low power. What I'm confused about is how to select switching transistors for this application. My PWM signal is a 5V square wave. Not very stiff - it's coming from a microcontroller.



I'm picturing the topology to be an NPN with it's emitter grounded, a resistive divider (of sorts) on it's output, and the base driven by the uC through a current limiting resistor. The output of the resistive divider would drive the bases of a complementary pair of BJTs. The complementary pair would be driving the FET's gate. So the first NPN is just a level shifter, and the pair is doing the driving. It might also make sense to have an amplifier BJT in between the level shifter and the driver. I'm just not sure.



First of all, is a FET inherently better than a BJT, or the other way around, for this? I feel like I typically see BJTs in this sort of circuit, but I could be mistaken.



Second - how do I choose a transistor for this? I see some BJT datasheets with rise and fall times speced, but I'm not clear on how they measure that and if that is the term that matters. Further, most datasheets don't even seem to include that.



Thanks so much!


-Michael


[...]

For level shifting, use n-p-n with emitter connected to uC via resistor and the base connected to Vcc.

What are the boost and sync FETs? What are the slew rates?

BTW, probably you can use something like IRS2011. Drive the boost fet with the low side of 2011, and the syncfet with the high side of 2011.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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how does that work? I assume you mean using that to level shift driving high side mosfets? When the uc pulls the resistor low any gate charge can be dissipated. If the uC one has the the exact same situation if the base voltage is higher than the uC voltage.

Am I missing something?

Hi Vladimir - thanks for the response. I'm a little confused about what you're describing - what advantage would such a setup offer over a more traditional approach like what I described? It seems to me that your collector current is severely limited that way since the PWM source is not stiff.

I'm currently planning on using the International Rectifier IRFR3806TRPBF (datasheet here:

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ata/irfr3806pbf.pdf )

That chip looks like it would do what I want. I'm really hoping for a discrete solution though. This is not for a high volume project so I don't care about cost of components, and I thought it'd be more fun and, since it's a personal project, fun is what matters most! :)

Thanks,

-Michael

Dear Michael,

I guess the design of the boost convertor for you will take about a day of my payed time. Let me know if you wish me to proceed with the design. The contact is at the web site.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Pay you to have my fun? Hah!

-Michael

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