In one hand-wired proto recently,(*) I was using an LM319N open-collector dual comparator to drive the !set and !clear inputs of one section of a 74VHC74A dflop.
The 319 was running off +-15V. By mistake, I wired the pull-up resistor on one section to +15 rather than +5. The circuit worked perfectly--I only noticed the blunder when I went to make a slight change to the ramp current source.
Abs max on both VDD and any input is +7V, which appears to be a fairly absurd underestimate of what the !clear input can comfortably manage, at least for a day or two. It didn't seem to be drawing any input current, either--at most a few dozen microamps.
Cheers
Phil Hobbs
(*) It was that highly linear ramp generator I was talking about in another thread. Swapping out the mylar cap for a polypropylene reduced the soakage tail on the ramp, but didn't eliminate it.
Mylar isn't too bad at this speed (1-100 Hz). The original version of this circuit had about a 200 us reset pulse, controlling the gate of a
2N7002 directly. The capacitor was a 330 nF, 200V mylar, and the discharge arrangement was that 2N7002 with a 20-ohm resistor in series. The ramp reset pulse was about 200 us, i.e. about 15 time constants. There was about a 2-ms tail following the reset. The polyprop ones are probably 3x tighter, but not orders of magnitude.
I have some polystyrenes in my drawer, but they're only available up to the early nanofarads. (I have a few NOS ones up to 10 nF.)
I made a little RC differentiator gizmo with a polystyrene cap and an OPA141, and verified that the rest of the ramp was linear to better than
12 bits, which was about the limit of the measurement. Making the reset pulse 10 ms wide fixed it completely.
Seems like the chip makers decide how tight they can make the spec without hurting sales.
Some engineers are reluctant to run parts at abs max, so guardband down. I figure the manufacturer has already guardbanded.
One interesting case is reverse biasing polarized capacitors, which is rarely specified.
Another is RF parts, where the abs max voltage is often the max suggested supply max, and it's assumed but not stated that the actual drain voltage will swing to 2x the supply.
It's inconvenient that there's so little indication of how the ratings are arrived at.
Wet electros appear fine when you exceed their voltage ratings by a smallish amount like 10%, but their lifetime drops very very rapidly with overvoltage.
Very inconvenient. I wonder how guardband standards emerge. It's kind of a regional cultural thing, I expect. I like to measure parts to see how conservative the max ratings are. I can recall only one opamp, a Harris HFA1130, that was rated 11 volts abns max and would die about there. 11 was an unusual number.
Polymers are interesting. I tested a bunch for a couple of months to make sure I could use them reverse biased.
One thing that the semi people can't be trusted about is mosfet max power and current.
FDD86367 is a dpak spec'd at 227 watts and 100 amps CW.
IR established industry standards for insane power claims. One of their TO247 fets claims 1000 amps and 1000 watts.
Sometimes the way to get extreme performance is to push a part or two. That's a calculated risk.
Let me start by saying that I'm not an expert in how one establishes absolute maximum specs, but I spent the last 2+ decades of my IC-design career using leading-edge analog processes, both junction-isolated and dielectrically-isolated, to design complex custom mixed-signal components. Our customers, large test equipment manufacturers who might use thousands of an expensive IC---> in each system <---, expected continuous system up-time measured in months. Customer-site failures were very expensive and made them VERY unhappy, especially if magic smoke got release in a clean room. You don't know joy until you've been on the ultimate receiving end of a call placed by the president of your customer's billion dollar corporation to the president of your billion-dollar employer.
The most obvious aspect of an absolute-maximum rating is "Does the part blow up RIGHT NOW?". But that's only part of it. A stress beyond some abs-max limit might not destroy the part, but might cause a parametric shift that pushes it out of spec. This failure may or may not be immediately apparent in any particular application. Repeated application of the excess stress might produce cumulative damage that will cause the circuit to fail some time down the road.
Input bias currents could go up (this applies to logic as well as to analog circuits like op-amps). Offset could increase. Output pulldown current could decrease. Protection clamps could be damaged or destroyed. Supply current could increase. Any given design might be relatively insensitive to some or all of these shifts, but the IC manufacturer can't know that and must assume that every guaranteed spec is critical. That's what drives the absolute-maximum specs.
For the processes I worked with, large numbers* of individual devices (transistors, capacitors, resistors, etc.) were subjected to thousands of hours of testing at varying stress levels. Measurements performed at set intervals looked both gross failures and parametric shifts. This was used to establish device limits.
*In the case of one particular new digital device type I remember, the number of individual devices tested was well into 6 digits, and NO failures were allowed. And even with that, we were required to build in error detection and correction.
As we designed, we would check that things like collector-base voltage, reverse Vbe, capacitor voltage, gate-source and gate-drain voltages, current density, and internal device temperature were never exceeded with the specified supplies under both static and dynamic conditions. [Our in-house simulator's abilities to do automatic checking are way beyond anything I've ever seen available in commercial simulators.] These checkers were run during EVERY simulation through the entire design process, from the smallest circuit block through the complete circuit. And we would typically guardband our absolute maximum limits as well.
The fact that a component in a prototype board didn't immediately fail in a dramatic way when you exceeded one of its abs-max limits is nice, but that's no way to design a production article.
I'm sympathetic to the chip makers, who have no control over what their customers do with their parts. (Some years back we had a regular poster 'miso', an IC designer with a bad attitude towards customers--I didn't like it much, but that doesn't mean he had no excuse.) I'm also glad for the amount of effort that goes into that sort of stuff.
However, at least some customers are also vaguely competent, and it's frustrating to have zero insight into how such specs are arrived at, because sometimes there are excellent reasons for exceeding some of them (rf transistors' BV_CEO, for instance) and staying miles away from others (MOSFET max current and dissipation).
My experience of exceeding semiconductor temperature specs suggests that the difference between say an otherwise identical 125'C part and an 85'C part is twofold:
Yes, a long time ago when TI still had FAEs in the UK I was told that their A-grade op-amps were exactly the same as the rest apart from extra testing. Apparently they printed the -A designation BEFORE testing them. If they failed, they got thrown away. This was cheaper than having branches in the production line! It worked because most parts were good enough to be A-grade.
Believing that two parts with the same type number are the same is a form of category error, similar to "democratic" and "Democratic Republic of Congo". ;)
The poster children are the various flavors of TLV431--check out the stability boundaries for On Semi vs. Diodes. ;)
Sure, they don't create a new part, typically. But they test them separately. I'm more familiar with digital devices, where the timing characteristics vary with temperature. So buying a higher temperature range device is the same as buying a faster device. In fact, they often sell them as speed 1 at commercial temp, but speed 2 at industrial temp, all in the same part number, "C1/I2".
Same silicon, different testing and also the parts come from a different position on the bell curve. Although, some Xilinx guys have pointed out that if their process doesn't have a high pass rate at the fastest speed grade, they have done something wrong. Fallouts are mostly defects, rather than process variations.
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