horrible development

You guys'll love this story.

Working at a large asian videoscreen company on some EMI issues, I was asked to look at a comms problem late in the afternoon. an I2C connection had mysteriously stopped working. The actual circuit uses a HC4053 to switch the external I2C between a couple of different things. And it was refusing ot output a logic zero, which upset the downstream logic.

A bit of probing with a scope showed the 3.3V chip have 4V outputs. Luckily the schematic used useful supply names like Vcc1 and Vcc2, and also used "hidden" supply connections, making it almost impossible to figure out what chip had what supply voltage. So I did it with a DMM on beep.

Turns out the dangly wires are 5V, but all the innards are 3V3. And of course there was no thought put into voltage level translation (note: they have sold hundreds of millions of dollars of these things).

At the engineering management meeting the next morning, the chief engineer gave his report, which basically said faulty 4053 chips were the root cause. And his solution was:

- desolder faulty chip

- cut trace under IC

- re-solder faulty chip (IM NOT KIDDING)

- add dangly wires

- tack an OR gate on top of another chip

- use the OR gate to "buffer" the non-zero signal, to get a nice clean zero.

The owner of the company asked for my thoughts, at which point I gave a short lecture on whats inside ICs, what can happen when current is bunged thru the protection diodes (summary: anything, but always bad), and how the circuit was designed to force it to happen.

At lunch later that day, I was asked where I got my doctorate. They were astounded to discover I didnt have one, and that I didnt even bother finishing my ME thesis (somebody offerred to triple my pay, so I emigrated instead).

I ended up doing a detailed review of how often this occurred within the design. The answer? hundreds of times. One high-speed data chip had about 35 such connections; the resultant DC power was significant, although the IC at least didnt flip out.

Although the funniest was the FPGA, which had separate Vccio pins that could have been tied to 5V, but werent!

the relevant IIC 5V output had a series resistor anyway, so the kludge involved increasing it a bit, and tacking on a shunt resistor.

and the moral of the story is:

NEVER hide the power supply connections on a schematic, and ALWAYS use sensible names for power supplies, like +5V_iso

which at least gives a peer-reviewer a chance.

Cheers Terry

Surely it's common sense not to put signals through ESD protection diodes in the first place? And even if it works with one brand of chips, what happens if Purchasing switches to another supplier?

If I specify brand X, they buy brand X.

John

Poor dumb little me. I would have complied with the Fairchild "absolute maximum" spec for the inputs (0.5 volts beyond the rails). I guess that's what comes from thinking inside the box.

Could you just do a virtual earth with the opamp, and scale the input resistors? Use the parallel diodes on the inputs of the mux to limit the volts when the switch is disconnected

martin

Well, like I said, we knew we were rushing this design. An 8-channel DDS synthesizer VME module, with a 68K CPU and two fpga's, one a BGA, works on first etch with one jumper and two diodes. So shoot me.

John

On a sunny day (27 Feb 2007 12:56:49 -0800) it happened "Richard Henry" wrote in :

I would rule that out from the start, clipping diodes, as the distortion generated may make its way back to the driving source. Just use some sort of (semiconductor) switch to short that input in not selected.

selected.

Maybe one of those little single-gate bilateral switches. Hard to hack in as a fix, but I've done it with AWG39 magnet wire and epoxy.

Best regards, Spehro Pefhany

I haven't looked at all the posts with regards to this problem, so please forgive me if I'm reposting someone else's answer.

Since the bus is common to both inputs, except with the attenuation, you will be getting 25volts at the 4:1 input when the bus is at 100volts. This vastly exceeds the maximum input voltage of this device when you're only supplying it with +/- 5V DC.

Increase the attenuation of the 4:1 input to 10:1, and you shouldn't have any more problems.

No wonder you're damaging the input protection diodes and getting unwanted feedthrough. Got nothing to do with the chip manufacturing processes.

regards David

selected.

The 4:1 voltage divider is 100k to 33.2k, into the mux of the BIST (built-in self-test) ADC. Each of the eight 50-ohm DDS outputs (which can be as high as 100 volts p-p) can be relay-switched from the user connector to a test bus, and it's this bus that drives the two dividers into the mux. There's also a frequency counter hooked to the test bus, and some other mux inputs to the adc. So a tiny amount of distortion wouldn't matter.

The BIST allows the user to poke a macro command into a VME register and have the module pretty much test itself... takes about 10 seconds. This is a functional test, not really an accuracy test, so the failure limits are pretty broad, 0.1% on frequency and 3% on amplitude. Each channel also has six SSRs and a switchable isolation transformer in its output, and BIST tests all of that, too. The code was an immense pita. I'm still clocking the SPI adc one time more than the datasheet says I should, and I guess I'll never know why.

Maybe I'll just use a DG508 next rev, powered by +-12.

John

Of course I could use a single high-ratio attenuator, 20:1 actually, but then I'd be throwing away low-end resolution. I considered that option, but then I'd have to change the code, and open up my test limits.

There's less than 500 uA going into the esd diodes, and nothing is being damaged; I'm just getting a gain error. Hell, if I were a real hack, I could just change my test limits.

As Jim figured out, the 0.6 volt swing past the rails is likely turning on one of the cmos pass transistors and dumping that current into the analog output node. I'm glad I understand that now.

They could have designed the chip so that this doesn't happen.

John

Not easily. The MUX is specified as bi-directional.

...Jim Thompson

Well, Rob was harassing me about the inelegance of my dual-schottky kluge, so we came up with this:

which clamps the swing to about +3.9 and -3.5, fine for the +-3.3 range of the adc and fine for the +-5 range of the mux.

Don't you just hate it when underlings are right?

John

Excellent. Buy that man a beer!

Cheers Terry

Qui craint des collaborateurs éminents, n'est pas un chef.

Jeroen Belleman

Perhaps using a different device would be a more optimal solution, particularly for the higher voltages experienced.

Where I worked previously, we designed an automatic test jig that utilised NAIS AQW212A PhotoMOS devices, and they worked very well. That series had devices that worked up to 600V @ 40mA load current. The last price I obtained from Mouser (early 2006) was roughly US$2 each for the '212A's.

Regards David

Hmm, possibly quite nice, but didn't you mention wanting to go to higher frequency BIST eventually? What's the capacitance of that zener?

Cheers,

Phil Hobbs

That was a bit much for my rusty high school French, but Babelfish gives

"Who fears eminent collaborators, is not a chief."

which looks pretty good for a computer translation. Unless, of course, they cheated by including common sayings.

But yes, it takes guts to brainstorm.

John

Yup. We're planning versions of this module up to 25 MHz at least. The crystal clock is 32 MHz and the fpga can clock multiply... we're currently plunking along at 64 MHz internally, which should make decent 16 MHz sinewaves. The dacs are good for 140 MHz, and the analog stuff downstream of the dacs is plenty fast.

My trusty AADE meter reports 53 pF at zero bias, so it should be a bunch less as used here. This is a regular 1N751-series type.

I wonder if anybody makes really tiny geometry zeners.

But one of the mux inputs is the output of an AD8361 integrated RF detector, currently unstuffed. We figure that if we do a serious hf version, we'll use that as the amplitude detector at the higher frequencies. The dinky ADS7866 serial adc wouldn't give us useful samples above about a hundred khz anyhow.

A b-e junction could be a very low-c zener, but they tend to run closer to 5 volts.

The BIST philosophy is to detect most reasonable field failure modes, knowing that a serious production test was once done. So I'm checking amplitudes at 10 KHz (software rectifying the samples), checking frequency (separate xo as ref, counter in the fpga), and verifying all the SSR transformer switching paths and such.

I could post the BIST schematic is anyone is interested. I posted a pic of the board to abse a few weeks ago.

I wish more people would post the stuff they're actually designing, instead of asking cryptic questions.

John